Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: There is provided a nonvolatile semiconductor memory comprising: a memory bock composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and means for updating a content of the register by a data processor coupled to the register. By using this updating means to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.

Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A data processor which performs in parallel a comparison process of n (which is an integer 2 or more)--sets first size data a elements by logical add operation between data elements in executing a first instruction for processing simultaneously number of n first size data elements, and performs a comparison process of one-set second size data elements by logical product operation of the compared results of whole data elements in executing a second instruction for processing individually second size data elements whose size is n times of said first size.