Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method of operating a user device includes: receiving a command from a user to power on the user device; determining whether the user device is located within a restricted zone through accessing a key server located within the restricted zone by a first monitoring entity of the user device before an operating system of the user device is executed, wherein the key server is configured to store a key for encrypting or decrypting the user device; and granting access of the user to the user device by the first monitoring entity in response to determining the user device as being within the restricted zone through successfully accessing the key server.

Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: A method for preparing a recycled plastic includes the steps of: (a) mixing a waste plastic with a depolymerizing agent, followed by subjecting the waste plastic to a depolymerization reaction, so as to obtain a depolymerized product; (b) mixing the depolymerized product with a first polyether polyol to obtain a first mixture, followed by subjecting the first mixture to a polymerization reaction, so as to obtain a polymeric diol mixture; and (c) mixing the polymeric diol mixture with a second polyether polyol, a multi-functional isocyanate, and a solvent to obtain a second mixture, followed by subjecting the second mixture to a reaction, thereby obtaining the recycled plastic having a carbamate group. A recycled plastic prepared by the aforesaid method, a non-porous film or a microporous film obtained from the recycled plastic, and a composite fabric including the non-porous film or the microporous film are also provided.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A power supply unit provides an output voltage to supply power to a load. The power supply unit includes an over-power protection circuit, and the over-power protection circuit includes a switch, a first resistor and a second resistor. When the output voltage is at a first level, the over-power protection circuit turns on the switch according to the output voltage at the first level to provide a first resistance value based on the first resistor and the second resistor in parallel, so as to adjust the over-power protection value of the power converter to a first value. When the output voltage is at the second level, the over-power protection circuit turns off the switch according to the output voltage at the second level to provide a second resistance value of the second resistor, so as to adjust the over-power protection value to a second value.

Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Abstract: An electronic device and a method for calibrating a temperature related scattering matrix (S-matrix) of a temperature sensitive device are provided. The electronic device includes a temperature sensitive device for receiving a forward signal and a reverse signal corresponding to a desired signal and a calibration kit for providing a switchable impedance. During a first phase, the electronic device operates in a first temperature, and multiple first calculation results are calculated according to the forward signal and the reverse signal by setting the switchable impedance to be multiple impedances, respectively. During a second phase, the electronic device operates in a second temperature, and multiple second calculation results are calculated according to the forward signal and the reverse signal by setting the switchable impedance to be the multiple impedances, respectively.

Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Abstract: A wireless local area network (WLAN) system includes a first Wi-Fi device and at least one second Wi-Fi device. When the first Wi-Fi device and the at least one second Wi-Fi device receive an interference signal that occupies a current operation channel of the first Wi-Fi device and a current operation channel of the at least one second Wi-Fi device, the first Wi-Fi device performs channel switching upon the current operation channel of the first Wi-Fi device, and the at least one second Wi-Fi device performs channel switching upon the current operation channel of the at least one second Wi-Fi device.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: A process gas is flowed from an input metal gas line that is electrically grounded to an output metal gas line via a connecting tube which is electrically insulating. Couplings between the metal gas lines and the connecting tube are sealed with gas couplings. Each gas coupling includes a sealing gasket, and a clamp compressing the sealing gasket between an end of the respective metal gas line and a corresponding end of the connecting tube. The process gas is delivered to a semiconductor processing tool via the output metal gas line. At least one operation is performed at the semiconductor processing tool that utilizes both the process gas delivered to the process tool via the output metal gas line and an electrical voltage of at least 2 kilovolts. The connecting tube may be sapphire. The sealing gaskets may be polytetrafluoroethylene (PTFE) sealing gaskets.

Abstract: A method includes a number of operations. An interlayer dielectric (ILD) layer is formed over a source/drain region on a substrate. A source/drain contact extending through the ILD layer to electrically connect with the source/drain region is formed. An air gap extending through the ILD layer is formed. An implantation energy absorption dielectric layer is formed over the ILD layer. An implantation process is performed on the implantation energy absorption dielectric layer, wherein the implantation process causes the ILD layer expands to seal the air gap. A first implant-free dielectric layer is formed over the implantation energy absorption dielectric layer. A second implant-free dielectric layer is formed over the first implant-free dielectric layer. A source/drain via extending through the second implant-free dielectric layer, the first implant-free dielectric layer, and the implantation energy absorption dielectric layer to the source/drain contact is formed.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: An electronic device and a method for estimating scattering parameters of a two-port network are provided. The electronic device includes a two-port network, a directional coupler, an input calibration kit placed in front of the two-port network, an output calibration kit placed behind the two-port network, and a control switch connected between the directional coupler and the two-port network. The directional coupler transmits a desired signal and receives a forward signal and a reverse signal from the two-port network. When the control switch is turned off, input calculation results are calculated according to the forward signal and the reverse signal by controlling the input calibration kit. When the control switch is turned on, output calculation results are calculated according to the forward signal and the reverse signal by controlling the output calibration kit. The scattering parameters are estimated according to the input calculation results and the output calculation results.