Patents by Inventor Kuo-an Chen
Kuo-an Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099086Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.Type: ApplicationFiled: November 17, 2023Publication date: March 21, 2024Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
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Publication number: 20240097080Abstract: A light emitting module includes a carrier, a light emitting element, a reflection layer, and a fluorescent layer. The light emitting element is disposed on the carrier. The reflection layer is disposed on the carrier and surrounds the light emitting element. The fluorescent layer covers at least part of the light emitting element. The disadvantages of over broad light emitting angle and low illuminance may be solved. Comparing with the related art, the present disclosure achieves an object of increasing the illuminance by at least 10%.Type: ApplicationFiled: July 6, 2023Publication date: March 21, 2024Inventors: Chen-Lun HSING CHEN, Jung-Hao HUNG, Ya-Yu HUNG, Yi-Ting KUO
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Patent number: 11936381Abstract: A switch module with an automatic switching function and a method for automatically switching the switch module according to the load, wherein a first comparator and a second comparator are configured to automatically determine whether the load is light or heavy according to the voltage divided by a first resistor and a second resistor and the voltage of a source resistor, thereby generating a voltage control signal. A plurality of transistors are configured to receive a gate input signal according to the voltage control signal, thereby selectively bringing a GaN transistor or a MOSFET transistor in a conducting state. In this way, the output quality and efficiency of the power supply at light and heavy loads can be improved according to the characteristics of different transistors.Type: GrantFiled: October 19, 2022Date of Patent: March 19, 2024Assignee: POTENS SEMICONDUCTOR CORP.Inventors: Ching Kuo Chen, Wen Nan Huang
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Publication number: 20240088899Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: SHAO-HUAN WANG, CHUN-CHEN CHEN, SHENG-HSIUNG CHEN, KUO-NAN YANG
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Publication number: 20240086021Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Chia-Hsiung CHANG, Yang-Chen CHEN, Kuo-Chang SU, Hsia-Ching CHU
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Patent number: 11926017Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.Type: GrantFiled: May 5, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Charlie Wang, Yu-Ping Tseng, Y. J. Chen, Wai-Ming Yeung, Chien-Shen Chen, Danny Kuo, Yu-Hsuan Hsieh, Hsuan Lo
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Patent number: 11927871Abstract: Disclosed are near-eye displaying methods and systems capable of multiple depths of field imaging. The method comprises two steps. At a first step, one or more pixels of a self-emissive display emit a light to a collimator such that the light passing through the collimator is collimated to form a collimated light. At a second step, the self-emissive display provides at least one collimated light direction altering unit on a path of the light from the collimator to change direction of the collimated light to enable the collimated light from at least two pixels to intersect and focus at a different location so as to vary a depth of field.Type: GrantFiled: March 1, 2018Date of Patent: March 12, 2024Assignee: HES IP HOLDINGS, LLCInventor: Tai-Kuo Chen
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Patent number: 11921434Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: GrantFiled: December 15, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11924401Abstract: A system and method for displaying a 3D image with depths, which utilize at least one light signal generator to sequentially generate multiple light signals(S100) and at least one optical assembly to receive the multiple light signals from the at least one light signal generator, and project and scan the multiple light signals within a predetermined time period to display the 3D image in space(S200). Each pixel of the 3D image is displayed at a position by at least two of the multiple light signals to a viewer's eye, paths or extensions of the paths of the at least two light signals intersects at the position and at an angle associated with a depth of the pixel, and the predetermined time period is one eighteenth of a second. Accordingly, the advantages of simplified structure, a miniatured size, and a less costly building cost can be ensured.Type: GrantFiled: October 29, 2019Date of Patent: March 5, 2024Assignee: HES IP HOLDINGS, LLCInventor: Tai Kuo Chen
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Publication number: 20240074206Abstract: A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Chen CHANG, Kuo-Chi TU, Tzu-Yu CHEN, Sheng-Hung SHIH
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Publication number: 20240073981Abstract: The present disclosure provides a control method applied to a first electronic device and a second electronic device in a physical environment. The first electronic device and the second electronic device are configured to communicate with each other through a first wireless connection established between the first electronic device and the second electronic device. The control method includes: by at least one of the first electronic device and the second electronic device, determining whether to update a map of the physical environment; and in response to a determination to update the map of the physical environment, establishing a second wireless connection different from the first wireless connection between the first electronic device and the second electronic device, wherein the second wireless connection is configured to transmit a map updated data, and the map updated data is configured to update the map of the physical environment.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Kai-Hsiu CHEN, WeiChih KUO, Wei-Shen OU
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Publication number: 20240069299Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
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Publication number: 20240074041Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.Type: ApplicationFiled: August 16, 2023Publication date: February 29, 2024Inventors: Gwo-Shyan Sheu, Kuo-Liang Huang, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma
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Publication number: 20240071722Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
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Patent number: 11912837Abstract: The present disclosure provides a thin film including a first thermoplastic polyolefin (TPO) elastomer which is anhydride-grafted. The present disclosure further provides a method for manufacturing the thin film, a laminated material and a method for adhesion.Type: GrantFiled: August 2, 2021Date of Patent: February 27, 2024Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chi-Chin Chiang, Wen-Hsin Tai, Ming-Chen Chang
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Patent number: 11876189Abstract: A battery module for use in a battery system is operable in a bottom mode, a top mode or a middle mode during an enabled state. The battery module includes a battery unit and a battery control circuit. The battery unit which includes at least one battery generates a battery unit voltage between a positive terminal and a negative terminal of the battery unit. The battery control circuit is powered by the battery unit voltage and is configured to control the battery unit. The battery control circuit includes an enable terminal, an upstream input terminal, an upstream output terminal, a downstream input terminal, and a downstream output terminal. When the enable terminal is at an operation enabling level, or when the upstream input terminal is at an upstream enabling level, the battery module enters the enabled state.Type: GrantFiled: February 4, 2020Date of Patent: January 16, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Wei-Hsu Chang, Hao-Wen Chung, Chung-Hui Yeh, Kuo-Chen Tsai
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Patent number: 11854898Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: May 17, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20230368950Abstract: A packaging structure with a magnetocaloric material, comprising a substrate, a plurality of electrical connection structures, a die, and a sealing compound. A magnetocaloric material is added to the substrate. The die is electrically connected to the substrate through the electrical connection structures, and then encapsulated with the sealing compound. When the packaging structure is turned on, the magnetocaloric material in the substrate creates a magnetocaloric effect, which can not only take away the temperature of the packaging structure through magnetic refrigeration, but also increase the temperature difference between the packaging structure and the outside, thereby improving the efficiency of heat dissipation.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Wen Nan Huang, Ching Kuo Chen, Chih Ming Yu, Hsiang Chi Meng, I Ming Lo
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Publication number: 20230360553Abstract: A method for creating a modified flight simulation program for a flight simulation system includes: obtaining a demonstration flight record associated with a preset track route of a virtual airplane; generating an add-on content pack for the flight simulation program based on the demonstration flight record; and merging the add-on content pack to the flight simulation program to create a modified flight simulation program. The generation of the add-on content pack includes: mapping the preset track route to geographical coordinate data in the real world, creating a first program module associated with a demonstration mode enabling a demonstration virtual flight along the preset track route, creating a second program module associated with an assisted flight mode enabling user control for a virtual flight within a free-flight space, and creating the add-on content pack that includes the first and the second program modules.Type: ApplicationFiled: May 3, 2023Publication date: November 9, 2023Inventors: Kuo-Chen Chen, Po-Hsiung Chang, Ying-Yun Chang, Wan-Yu Chung, Che-Jen Yeh