Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.

Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.

Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Abstract: A film application apparatus includes a first base configured to couple a film material and a second base rotatably coupled to the first base. The first base defines an opening and two through holes on opposite side of the first base, the through holes communicate with the opening. The second base defines a receiving chamber and the receiving chamber is configured for accommodating a work piece. The film application apparatus further includes a pressing component inserted through the first base, the pressing component penetrating through the opening from the two through holes for pressing the film material against to a face of the work piece.

Abstract: An organosilicate polymer is used as mandrel in a two exposure double patterning process. The mandrel layer is formed from the organosilicate polymer and is patterned with a first etching process. Spacers are formed adjacent the mandrel using low temperature process. The spacer material can be a low temperature oxide. The mandrel layer is then further pattered with a second lithographic etching process. A hard mask layer is then printed with a pattern defined by the spacers and the mandrel. The hard mask can be TiN. The process provides a simplified method of double patterning that eliminates the need for a capping layer over the hard mask.

Abstract: In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.

Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.

Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.

Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.

Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

Abstract: A single piece type capacitive touch panel uses an etching process to form a frame on periphery of a transparent substrate. An icon layer is disposed in the frame by printing or sputtering. The icon layer completely fills the frame. In addition, one side face of the icon layer has an optical film. Accordingly, the structure of utilizing the frame to combine the icon layer can greatly increase the visible area, enhance the flatness, and avoid thicker thickness caused by climbing effect on curved corner of the conventional icon layer, or Mura phenomenon caused by the stacked structure at the side of the conventional icon layer.

Abstract: A touch sensor device with increased transmittance, increased sensitivity and decreased thickness is disclosed. The touch sensor device includes a substrate. The substrate, from bottom to top, sequentially includes a bottom conductive layer, a bottom insulation layer, a top conductive layer, an electrode layer, a top insulation layer and a substrate material layer. The bottom conductive layer can shield external electromagnetic interference and act as a ground. The bottom insulation layer is provided with an insulation effect. The top conductive layer is used for sensing a touch operation to generate a sensor signal. The electrode layer includes a plurality of first electrode lines, a barrier layer and a plurality of second electrode lines. The top insulation layer is provided with an effect for preventing electrostatic discharge. The substrate material layer is used for protecting the touch sensor device.

Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.

Abstract: An external input device is disclosed. The external input device comprises an upper case, a touch sensor module, a control module, a lighting module, a transfer module, a transparent substrate, and a lower case. The upper case comprises a visible region and a shielding region; the touch sensor module is provided under the upper case; control module is provided under the shielding region; the lighting module is provided on the control module; the transparent substrate is provided under the touch sensor; and the lower case is used for sitting the touch sensor module, the control module, the lighting module, the transfer module, and transparent substrate, and integrates with the upper case. The external input device can be used for performing pointing mode and key-in mode to replace the functions of mice, touch panel, and partial functions of keyboards, and the external input device is easy to switch between the modes for users.

Abstract: An improved method of fabricating a contact hole is provided. A semiconductor substrate is provided wherein a transistor is formed on the substrate. A dielectric layer is formed over the substrate. A patterned mask layer with an opening is formed on the dielectric layer. An UV curing treatment is performed on the mask layer. The dielectric layer is anisotropically etched using the mask layer as a mask to form a contact hole in the dielectric layer.

Abstract: A method for etching a doped polysilicon layer. A first doped polysilicon layer of a first conductive type and a second doped polysilicon layer of a second conductive type are formed. An etching process is performed to pattern the first doped polysilicon layer and the second doped polysilicon layer. The etching process includes a first main etching step and a second main etching step. The etching pressure of the first main etching step is lower than the etching pressure of the second main etching step.

Abstract: An improved method for oxide etching that uses of a mixture of etching gases including CF.sub.4 /C.sub.4 F.sub.8 /CO/Ar/N.sub.2 such that etching selectivity between oxide and other materials can be increased. Furthermore, the addition of a cleaning step between etching operations in this invention is able to remove most of the deposited polymers formed during the etching operation, hence etching stop phenomenon can be prevented. Also, the presence of N.sub.2 in the etching gas mixture is able to prevent the formation of polymers on the sidewalls of an etched contact opening. Hence, when metal is subsequently deposited into the opening to form a self-aligned silicide layer, there are few polymers to react with the metal atoms to form a layer of high resistance material on the sidewalls of the opening. Thus, reliability of the device can be maintained.