Patents by Inventor Kuo-An Liu
Kuo-An Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250089332Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: ApplicationFiled: November 27, 2024Publication date: March 13, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
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Patent number: 12218074Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.Type: GrantFiled: June 9, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Publication number: 20250015007Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.Type: ApplicationFiled: July 6, 2023Publication date: January 9, 2025Inventors: Yu-Chung Lai, Ying-Yao Lai, Chen-Chiu Huang, Hsiang-Ku Shen, Dian-Hau Chen, Kuo-An Liu, Tzu-Ting Liu
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Patent number: 12183805Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: GrantFiled: May 28, 2021Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
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Patent number: 12174545Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: GrantFiled: July 28, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien, Gwan-Sin Chang, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20240379593Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.Type: ApplicationFiled: July 12, 2024Publication date: November 14, 2024Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
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Patent number: 12087714Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.Type: GrantFiled: January 31, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
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Publication number: 20240096818Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang
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Publication number: 20230367225Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Tai-Yu CHEN, Sagar Deepak KHIVSARA, Kuo-An LIU, Chieh HSIEH, Shang-Chieh CHIEN, Gwan-Sin CHANG, Kai Tak LAM, Li-Jui CHEN, Heng-Hsin LIU, Chung-Wei WU, Zhiqiang WU
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Publication number: 20230317629Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.Type: ApplicationFiled: June 9, 2023Publication date: October 5, 2023Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Publication number: 20230317829Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang WU, Kuo-An LIU, Kai Tak LAM, Meng-Yu LIN, Chun-Fu CHENG, Chieh-Chun CHIANG, Chun-Hsiang FAN
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Patent number: 11768437Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: GrantFiled: July 18, 2022Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien, Gwan-Sin Chang, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 11715702Abstract: In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure.Type: GrantFiled: August 4, 2021Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Publication number: 20230145953Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.Type: ApplicationFiled: January 31, 2022Publication date: May 11, 2023Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
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Publication number: 20220350257Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Tai-Yu CHEN, Sagar Deepak KHIVSARA, Kuo-An LIU, Chieh HSIEH, Shang-Chieh CHIEN, Gwan-Sin CHANG, Kai Tak LAM, Li-Jui CHEN, Heng-Hsin LIU, Chung-Wei WU, Zhiqiang WU
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Patent number: 11392040Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: GrantFiled: March 5, 2021Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien, Gwan-Sin Chang, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20210366840Abstract: In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Publication number: 20210349396Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: ApplicationFiled: March 5, 2021Publication date: November 11, 2021Inventors: Tai-Yu CHEN, Sagar Deepak KHIVSARA, Kuo-An LIU, Chieh HSIEH, Shang-Chieh CHIEN, Gwan-Sin CHANG, Kai Tak LAM, Li-Jui CHEN, Heng-Hsin LIU, Chung-Wei WU, Zhiqiang WU
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Patent number: 11139341Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.Type: GrantFiled: April 10, 2019Date of Patent: October 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-An Liu, Chung-Cheng Wu, Harry-Hak-Lay Chuang, Gwan-Sin Chang, Tien-Wei Chiang, Zhiqiang Wu, Chia-Hsiang Chen
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Publication number: 20210305409Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: ApplicationFiled: May 28, 2021Publication date: September 30, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN