Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.

Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: A method for selectively chemically reducing CO2 to form CO includes providing a catalyst, and contacting H2 and CO2 with the catalyst to chemically reduce CO2 to form CO. The catalyst includes a metal oxide having a chemical formula of FexCoyMn(1-x-y)Oz, in which 0.7?x?0.95, 0.01?y?0.25, and z is an oxidation coordination number.

Abstract: A package structure includes a bonding substrate, an integrated circuit, and a heat sink metal. The integrated circuit includes an active region facing the bonding substrate. The heat sink metal is located between the bonding substrate and the active region of the integrated circuit. The heat sink metal is electrically insulated with the integrated circuit.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: Disclosed herein are ACE2-Fc fusion polypeptides that contain at least one binding site for a spike protein of a coronavirus and methods of using such for therapeutic and/or diagnostic purposes. Also provided herein are methods for producing such fusion polypeptides.

Abstract: The present invention is related to a clipped testing device, comprising a first clamping member, a second clamping member, a shaft, and a conducting member. The first clamping member has a first pin joint member and a first substrate, the second clamping member has a second pin joint member and a second substrate. The shaft detachably pivoted to a first pin joint member and a second pin joint member. The conducting member is disposed on the first clamping member and is located between the first substrate and the second substrate. The conducting member has an upper surface and a lower surface. The lower surface of the conducting member faces toward the first substrate, and at least a part of the conducting member is wavy-shaped and has a first scraping structure on the upper surface thereof.

Abstract: A light-emitting module structure includes a substrate, a plurality of light-emitting diodes (LEDs) disposed on the substrate, and a light-guiding layer covering the light-emitting diodes. The light-guiding layer has an upper surface, the upper surface has a plurality of recesses, and the recesses are above the light-emitting diodes or between the light-emitting diodes. This light-emitting module structure can improve the brightness and uniformity of the light-emitting module.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: A method for identifying and selecting an object in a virtual or real environment is disclosed. The method comprises: determining a target finder area, at a computing device, within an area displayed by the user interface based on a user profile; determining a list of one or more objects within the target finder area; and presenting one or more of the determined list of one or more objects on the user interface.

Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: A light-emitting module structure includes a substrate, a plurality of light-emitting diodes (LEDs) disposed on the substrate, and a light-guiding layer covering the light-emitting diodes. The light-guiding layer has an upper surface, the upper surface has a plurality of recesses, and the recesses are above the light-emitting diodes or between the light-emitting diodes. This light-emitting module structure can improve the brightness and uniformity of the light-emitting module.

Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.

Abstract: A light-emitting module structure includes a substrate, a plurality of light-emitting diodes (LEDs) disposed on the substrate, and a light-guiding layer covering the light-emitting diodes. The light-guiding layer has an upper surface, the upper surface has a plurality of recesses, and the recesses are above the light-emitting diodes or between the light-emitting diodes. This light-emitting module structure can improve the brightness and uniformity of the light-emitting module.

Abstract: The disclosure is related to a battery formation system and probe supporting structure thereof. The battery formation system includes a base, a holder, a probe supporting structure and at least one probe. The base is adaptive to bear at least one battery, and the holder is located on one side of the base. The probe supporting structure is disposed on the holder. The probe supporting structure has an air flow passage and at least one air discharge channel connected to each other, and an extension direction of the air flow passage intersects an extension direction of the at least one air discharge channel. The at least one probe is disposed on the probe supporting structure, and a probing end of the at least one probe and an air outlet of the at least one air discharge channel are located at a same side of the probe supporting structure.