Patents by Inventor Kuo-Chen Wang

Kuo-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190221366
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Publication number: 20190172517
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 6, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Publication number: 20190148066
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10290422
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10242726
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Publication number: 20190088658
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
  • Patent number: 10163909
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Patent number: 10153027
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Patent number: 10083734
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Publication number: 20180198719
    Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.
    Type: Application
    Filed: March 25, 2016
    Publication date: July 12, 2018
    Inventors: Tsung-Hsien TSAI, Kuo-Chen WANG, Wei-Feng WU, Wei-Tso TSAI, Yu-Han SHIH
  • Publication number: 20180131603
    Abstract: A network system control method includes intercepting a flow modification message sent by a controller from a network protocol path between a switch and the controller so as to obtain a new flow entry; accessing a flow table of the switch so as to obtain a plurality of flow entries; inserting at least one redundant flow entry according to the new flow entry and the plurality of flow entries; performing an aggregation operation to the new flow entry, the plurality of flow entries and the at least one redundant flow entry so as to generate a set of aggregated flow entries; and updating the flow table using the set of aggregated flow entries.
    Type: Application
    Filed: October 18, 2017
    Publication date: May 10, 2018
    Inventors: Yu-Ching Ye, Tzu-Yu Chao, Kuo-Chen Wang
  • Publication number: 20180102366
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Publication number: 20180083011
    Abstract: A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 22, 2018
    Inventor: Kuo-Chen Wang
  • Patent number: 9881924
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Patent number: 9859285
    Abstract: A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Chen Wang
  • Patent number: 9859284
    Abstract: A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: January 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Chen Wang
  • Publication number: 20170330882
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Publication number: 20170213837
    Abstract: A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.
    Type: Application
    Filed: September 1, 2016
    Publication date: July 27, 2017
    Inventor: Kuo-Chen Wang
  • Publication number: 20170213834
    Abstract: A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.
    Type: Application
    Filed: January 21, 2016
    Publication date: July 27, 2017
    Inventor: Kuo-Chen Wang
  • Patent number: 9674077
    Abstract: The invention discloses a vehicular communication system and a routing method thereof. The routing method includes the following steps. When a first relay node of the relay nodes, which locates in a last road slot of each of the road section, receives the route reply packet, the first relay node is configured to obtain a plurality of moving traces of a plurality of specific relay nodes according to the route reply packet; estimate at least one connection life period related to a plurality of specific road slots according to the moving traces; estimate at least one connection available interval of the specific road section according to the at least one connection life period; and append the at least one connection available interval to the route reply packet and forward the route reply packet.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: June 6, 2017
    Assignee: National Chiao Tung University
    Inventors: Yi-Ling Hsieh, Kuo-Chen Wang