Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: A semiconductor device includes first channel members, a first gate structure wrapping around each of the first channel members, a first epitaxial feature abutting the first channel members, second channel members, a second gate structure wrapping around each of the second channel members, a second epitaxial feature abutting the second channel members, and an isolation feature has a first portion laterally stacked between the first and second gate structures and a second portion laterally stacked between the first and second epitaxial features. A width of the first portion of the isolation feature is larger than a width of the second portion of the isolation feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

Abstract: A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: A semiconductor device includes a substrate, an active structure, a first dielectric layer and a second dielectric layer. The active structure is formed on the substrate and includes an active channel sheet, wherein the active channel sheet has a first lateral surface. The first dielectric layer is formed above the active structure and has a recess, wherein the recess is recessed with respect to the first lateral surface of the active channel sheet. The second dielectric layer is formed within the recess and has a dielectric constant, wherein the dielectric constant is less than 3.9.

Abstract: A pixel structure is provided. The pixel structure includes a substrate, a photo detecting region, a first transfer gate, and a second transfer gate. The photo detecting region is in the substrate and has a first doping type. The first transfer gate includes a first portion in contact with a first side of the substrate and a second portion connected with the first portion and embedded in the substrate. An end of the second portion of the first transfer gate is adjacent to a side of the photo detecting region. The second transfer gate is adjacent to the first transfer gate. An end of the second transfer gate in the substrate is projectively over the photo detecting region. A method for manufacturing a pixel structure is also provided.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: An image sensor can be provided by: forming an array of image pixels on a semiconductor substrate; forming black level correction (BLC) pixels adjacent to the array of image pixels on the semiconductor substrate; forming a patterned layer stack over the array of image pixels and over the BLC pixels, wherein the patterned layer stack includes N repetitions of a unit layer stack in which N instances of the unit layer stack are repeated along a vertical direction; forming an optically transparent layer over an entirety of the patterned layer stack, wherein the optically transparent layer has a planar top surface; forming an infrared blocking material layer over the optically transparent layer; and patterning the infrared blocking material layer. A remaining portion of the infrared blocking material layer covers the BLC pixels, and does not cover the array of image pixels.

Abstract: A semiconductor image-sensing structure includes a reflective grid and a reflective shield disposed over a substrate. The reflective grid is disposed in a first region, and the reflective shield is disposed in a second region separated from the first region. A thickness of the reflective shield is greater than a thickness of the reflective grid.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures and a gate stack wrapped around the semiconductor nanostructures. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching one or more of the semiconductor nanostructures. The semiconductor device structure further includes an isolation structure continuously extending across edges of the semiconductor nanostructures.

Abstract: An image sensing apparatus is disclosed. The image sensing apparatus includes a pixel array and micro lenses disposed above the pixel array. The pixel array includes sensing pixels configured to capture minutia points of a fingerprint and positioning pixels configured to provide positioning codes.

Abstract: A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.