Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: The application relates to a light-emitting assembly including a substrate and an effective light-emitting region. The substrate has a first surface and a second surface that are opposite to each other and has a transparent material. The light shielding layer is disposed on the first surface of the substrate, and a first edge and a second edge of the light shielding layer are spaced apart from each other, thereby forming an opening. The effective light-emitting region is defined on the second surface of the substrate, and the effective light-emitting region and the first edge of the light shielding layer are offset by a first distance in a lateral direction. The first distance is associated with a refractive index of the substrate, a refractive index of a material in the opening of the light shielding layer, and a thickness of the substrate.

Abstract: A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.

Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.

Abstract: A semiconductor device and a method are provided. The semiconductor device includes a first semiconductor component, a bonding layer and a second semiconductor component. The first semiconductor component includes a first transistor formed on a substrate and a second transistor formed on the substrate and separated from the first transistor. The bonding layer is provided on the first semiconductor component. The second semiconductor component is provided on the bonding layer and includes an acoustic transducer. The acoustic transducer is controlled by the first transistor and the second transistor to execute a photoacoustic sensing. The acoustic transducer comprises a space gap and a least a portion of the space gap is surrounded by the bonding layer.