Patents by Inventor Kuo-Cheng Chiang

Kuo-Cheng Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985072
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Ting Pan
  • Publication number: 20210098605
    Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and a second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Pei-Hsun Wang, Kuo-Cheng Chiang, Lo-Heng Chang, Jung-Hung Chang, Chih-Hao Wang
  • Publication number: 20210098455
    Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first FET device disposed in the first region, and a second FET device disposed in the second region. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets stacked over the substrate and separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. In some embodiments, the fin structure has a first width, each of the nanosheets has a second width, and the second width is greater than the first width.
    Type: Application
    Filed: February 5, 2020
    Publication date: April 1, 2021
    Inventors: JIA-NI YU, KUO-CHENG CHIANG, LUNG-KUN CHU, CHUNG-WEI HSU, CHIH-HAO WANG, MAO-LIN HUANG
  • Publication number: 20210098609
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20210098302
    Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.
    Type: Application
    Filed: September 29, 2019
    Publication date: April 1, 2021
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210098456
    Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang
  • Publication number: 20210098304
    Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang
  • Publication number: 20210098573
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a fin protruding from the front surface, the fin including: a first semiconductor layer in proximal to the front surface, a second semiconductor layer stacked over the first semiconductor layer, a gate between the first semiconductor layer and the second semiconductor layer, and a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region laterally surrounding the fin, wherein the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including: a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section, wherein an absolute value of a derivative at the third section is greater than an absolute value of a derivative at the second section.
    Type: Application
    Filed: February 7, 2020
    Publication date: April 1, 2021
    Inventors: GUAN-LIN CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG, SHI NING JU, JUI-CHIEN HUANG
  • Publication number: 20210098459
    Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210098625
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
  • Publication number: 20210083079
    Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.
    Type: Application
    Filed: October 12, 2020
    Publication date: March 18, 2021
    Inventors: Kuo-Cheng Chiang, Carlos H. Diaz, Chih-Hao Wang, Zhiqiang Wu
  • Patent number: 10943830
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan
  • Patent number: 10943833
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
  • Publication number: 20210066136
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHIANG, Chung-Wei HSU, Lung-Kun CHU, Jia-Ni YU, Chih-Hao WANG, Mao-Lin HUANG
  • Publication number: 20210066294
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 4, 2021
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20210066137
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: July 10, 2020
    Publication date: March 4, 2021
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Patent number: 10937704
    Abstract: A method includes depositing a first conductive material on a first-type channel stack and a second-type channel stack, the first conductive material having a first workfunction, the first conductive material being formed between multiple layers of both the first-type channel stack and the second-type channel stack. The method further includes partially removing the first conductive material from the second-type channel stack such that the first conductive material remains between the multiple layers of both the first-type channel stack and the second-type channel stack and fully removing the first conductive material from the second-type channel stack.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Chih-Hao Wang, Mao-Lin Huang
  • Publication number: 20210057325
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20210057539
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Publication number: 20210057525
    Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang