Patents by Inventor Kuo-Cheng Chiang

Kuo-Cheng Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375936
    Abstract: A semiconductor device includes first and second n-type transistors and first and second p-type transistors. The first n-type transistor includes a first channel layer and a first portion of a high-k dielectric layer over the first channel layer. The second n-type transistor includes a second channel layer and a second portion of the high-k dielectric layer over the second channel layer, wherein the second portion includes a higher amount of an n-type dipole material than the first portion. The first p-type transistor includes a third channel layer and a third portion of the high-k dielectric layer over the third channel layer. The second p-type transistor includes a fourth channel layer and a fourth portion of the high-k dielectric layer over the fourth channel layer, wherein the fourth portion includes a higher amount of a p-type dipole material than the third portion.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 24, 2022
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20220376072
    Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 24, 2022
    Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20220367457
    Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220367463
    Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Jung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20220367462
    Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220367288
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Publication number: 20220367455
    Abstract: According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Kuan-Ting PAN, Yi-Ruei JHAN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20220367703
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Publication number: 20220367689
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20220367291
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Patent number: 11502034
    Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lo-Heng Chang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 11502168
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Hou-Yu Chen, Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang, Jia-Ni Yu, Lung-Kun Chu
  • Publication number: 20220359305
    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220359309
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
  • Publication number: 20220359397
    Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: LO-HENG CHANG, KUO-CHENG CHIANG, ZHI-CHANG LIN, JUNG-HUNG CHANG, SHIH-CHENG CHEN, SHI-NING JU, CHIH-HAO WANG
  • Publication number: 20220359652
    Abstract: A semiconductor device includes a substrate and a transistor. The transistor includes a first channel region overlying the substrate and a source/drain region in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region.
    Type: Application
    Filed: December 27, 2021
    Publication date: November 10, 2022
    Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi Ning JU, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG
  • Publication number: 20220359514
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Inventors: Jui-Chien HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG, Shi Ning JU, Guan-Lin CHEN
  • Publication number: 20220359725
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang
  • Publication number: 20220359513
    Abstract: A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: JIA-NI YU, KUO-CHENG CHIANG, LUNG-KUN CHU, CHUNG-WEI HSU, CHIH-HAO WANG, MAO-LIN HUANG
  • Publication number: 20220359764
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shi-Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Chih-Hao WANG