Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 ? to about 20 ?.

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.

Abstract: A method for manufacturing a semiconductor structure includes forming fins over a substrate. Each of the fins includes a base fin protruding from the substrate, and first semiconductor layers and second semiconductor layers alternating stacked over the base fin. The method further includes forming an isolation structure between the base fins, forming a hard mask layer over the isolation structure, and removing the second semiconductor layers, so that the first semiconductor layers and the hard mask layer are exposed in a gate trench. The method further includes forming a gate structure in the gate trench. The gate structure wraps around the first semiconductor layers and over the hard mask layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

Abstract: A semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure and a second gate stack over the second channel structure. The first gate stack and the second gate stack have a first work function layer and a second work function layer, respectively. The first work function layer and the second work function layer are made of a same material. The second gate stack has a first protruding portion and a second protruding portion, and each of the first protruding portion and the second protruding portion extends upwards and extend away from the second channel structure. The first protruding portion and the second protruding portion are spaced apart from each other, and half of the first gate stack is wider than the first protruding portion.

Abstract: A method for forming a nanosheet device is provided. The method includes epitaxially growing a conformal semiconductor layer from a first stack of semiconductor layers and a second stack of the semiconductor layers. Each of the first and second stack of semiconductor layers includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other. A space between the first and second stacks of semiconductor layers is filled with a dielectric fin. The conformal semiconductor layer and the second semiconductor layers may be removed. A metal gate structure is formed over the first semiconductor layers and filling openings created by removal of the conformal semiconductor layer and the second semiconductor layer. A process may be performed on the metal gate structure to form an isolation between the portions of the metal gate structure being separated by a patterning process.