Patents by Inventor Kuo-Cheng Ching
Kuo-Cheng Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12142635Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.Type: GrantFiled: May 10, 2021Date of Patent: November 12, 2024Assignee: Parabellum Strategic Opportunities Fund LLCInventors: Ka-Hing Fung, Kuo-Cheng Ching, Ying-Keung Leung
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Patent number: 12119266Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.Type: GrantFiled: May 2, 2023Date of Patent: October 15, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Cheng Ching, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu
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Patent number: 12107153Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.Type: GrantFiled: April 10, 2023Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12087636Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.Type: GrantFiled: June 1, 2022Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Shi Ning Ju, Chih-Hao Wang, Kuan-Ting Pan
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Patent number: 12057507Abstract: A method includes forming a SiGe layer over a substrate. A silicon layer is formed over the SiGe layer. The silicon layer and the SiGe layer are patterned to form a fin structure over the substrate. The fin structure includes a remaining portion of the SiGe layer and a remaining portion of the silicon layer over the remaining portion of the SiGe layer. A semiconductive capping layer is formed to cover the fin structure. A top portion of the semiconductive capping layer and the remaining portion of the silicon layer are oxidized to form an oxide layer covering the fin structure.Type: GrantFiled: May 12, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12034062Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.Type: GrantFiled: November 4, 2022Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
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Patent number: 12027625Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.Type: GrantFiled: November 28, 2022Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
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Publication number: 20240213313Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.Type: ApplicationFiled: March 1, 2024Publication date: June 27, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20240194675Abstract: A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.Type: ApplicationFiled: February 16, 2024Publication date: June 13, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng CHING, Shi-Ning JU, Chih-Hao WANG
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Publication number: 20240186184Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.Type: ApplicationFiled: February 12, 2024Publication date: June 6, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng CHING, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240178070Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Kuo-Cheng Ching, Ying-Keung Leung
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Patent number: 11972981Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.Type: GrantFiled: June 17, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
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Patent number: 11948839Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.Type: GrantFiled: November 1, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 11948970Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.Type: GrantFiled: December 2, 2019Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240105719Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin, Chih-Hao Wang
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Patent number: 11942476Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.Type: GrantFiled: July 15, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
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Patent number: 11942548Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20240096885Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
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Patent number: 11935921Abstract: A semiconductor device includes a substrate and a semiconductor structure over the substrate. The semiconductor device also includes a first dielectric structure over the substrate, and the first dielectric structure has a first height. The semiconductor device further includes a second dielectric structure over the substrate, and the second dielectric structure has a second height. The second height is smaller than the first height. In addition, the semiconductor device includes a first gate stack wrapped around the first dielectric structure, and the semiconductor structure and the second dielectric structure are spaced apart from the first gate stack. The semiconductor device includes a second gate stack wrapped around the second dielectric structure and the semiconductor structure, and the second gate stack is electrically isolated from the first gate stack.Type: GrantFiled: June 22, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240088145Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching