Patents by Inventor Kuo-Cheng Lu

Kuo-Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218164
    Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Hsien Yang, Wen-I Hsu, Kuan-Fu Lu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12211805
    Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Lu, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12120038
    Abstract: A switch and a scheduling method for packet forwarding of the same are provided. The switch includes a plurality of absorb queues, a plurality of egress ports, and an absorb scheduler. Each of the egress ports includes a plurality of egress queues that are respectively connected to one of the absorb queues that are different from one another. The scheduling method includes: generating a priority state for each of the egress queues of each of the egress ports; a packet forwarding priority state of each of the absorb queues is determined according to the priority state of each of the egress queues connected thereto; and the absorb scheduler selecting one of the absorb queues to send a packet stored therein to a target egress queue of a target egress port to be sent to, according to the priority state of each of the egress queues.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: October 15, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Kuo-Cheng Lu, Yung-Chang Lin, Yu-Mei Pan
  • Patent number: 11989130
    Abstract: A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: May 21, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Kuo-Cheng Lu
  • Publication number: 20240064102
    Abstract: A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.
    Type: Application
    Filed: March 13, 2023
    Publication date: February 22, 2024
    Inventors: Kuo Cheng LU, Chun-Ming LIU, Sheng Wen LO
  • Patent number: 11863449
    Abstract: A communication device which is configured to receive a data flow includes a monitor port and a packet processor. The monitor port is configured to receive a packet of the data flow. The packet processor is coupled to the monitor port, and the packet processor is configured to compute a digest value of the packet and compute an identification code of the packet according to the digest value of the packet, and the packet processor searches a status value associated with the identification code in a lookup table so as to determine whether a dropping event of the data flow is recorded.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Chun-Da Wu, Yu-Hsiu Lin
  • Patent number: 11831413
    Abstract: A time-division multiplexing (TDM) scheduler determines a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: November 28, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Yu-Mei Pan, Yung-Chang Lin
  • Patent number: 11765088
    Abstract: A method and a system for processing a data flow with an incomplete comparison process are provided. The method is implemented by a network device that includes a flow table and a flow filter in a memory thereof. A flow analyzing module is provided for analyzing and classifying packets of an input flow, and identifying an application category to which the input flow belongs. The flow table is queried according to a result of resolving the input flow for determining whether the input flow matches any flow entry of the flow table. The flow filter is queried if the input flow fails to match any flow entry of the flow table for determining whether features of the input flow match conditions of the flow filter. The input flow is processed accordingly, without needing to copy all flows that do not match the flow entries to the flow table.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: September 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Kuo-Cheng Lu
  • Patent number: 11722423
    Abstract: Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 8, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Min-Chang Wei, Chun-Ming Liu, Kuang-Yu Yen
  • Publication number: 20230169006
    Abstract: A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.
    Type: Application
    Filed: October 25, 2022
    Publication date: June 1, 2023
    Inventor: KUO-CHENG LU
  • Patent number: 11658837
    Abstract: A replication list table structure for multicast packet replication is provided. The replication list table structure includes a plurality of entries. Each one of the plurality of entries includes a first field, a second field, a third field and a fourth field. For each one of the plurality of entries, the first field is used to declare whether the entry is an end of a program execution, the second field is used to declare the fourth field as a first type field for indicating a switch how to modify a header of a multicast packet, or as a second type field for indicating the switch, while reading the list, to jump to another one of the plurality entries, and the third field is preset to the first type field for indicating the switch how to modify the header of the multicast packet.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 23, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Kuo-Cheng Lu, Mao-Lin Huang, Yung-Chang Lin
  • Publication number: 20230155946
    Abstract: The present invention discloses a mesh network system having data flow transmission sorting mechanism that includes station devices, mesh network devices and a portal network apparatus.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 18, 2023
    Inventors: CHIAO-YI LIN, KUO-CHENG LU
  • Publication number: 20230057059
    Abstract: A time-division multiplexing (TDM) scheduler determines a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 23, 2023
    Inventors: KUO-CHENG LU, YU-MEI PAN, YUNG-CHANG LIN
  • Patent number: 11575610
    Abstract: A data flow classification device includes a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit; but if the classification is not found in the lookup table, the forwarding circuit tags the packets with a predetermined classification, outputs the packets to the buffer circuit, and adds the information of the input flow to the lookup table. The configuring circuit determines a flow threshold according to a queue length of the buffer circuit and a target length, learns the traffic of multiple flows from the lookup table, determines the classifications of the multiple flows according to the comparison between the traffic and the flow threshold, and stores these classifications in the lookup table.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 7, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Min-Chang Wei, Chun-Ming Liu, Kuang-Yu Yen
  • Patent number: 11563691
    Abstract: Disclosed is a time-division multiplexing (TDM) scheduler capable of determining a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 24, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Yu-Mei Pan, Yung-Chang Lin
  • Publication number: 20230006930
    Abstract: A method and a system for processing a data flow with an incomplete comparison process are provided. The method is implemented by a network device that includes a flow table and a flow filter in a memory thereof. A flow analyzing module is provided for analyzing and classifying packets of an input flow, and identifying an application category to which the input flow belongs. The flow table is queried according to a result of resolving the input flow for determining whether the input flow matches any flow entry of the flow table. The flow filter is queried if the input flow fails to match any flow entry of the flow table for determining whether features of the input flow match conditions of the flow filter. The input flow is processed accordingly, without needing to copy all flows that do not match the flow entries to the flow table.
    Type: Application
    Filed: January 11, 2022
    Publication date: January 5, 2023
    Inventor: KUO-CHENG LU
  • Publication number: 20220231955
    Abstract: Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.
    Type: Application
    Filed: September 3, 2021
    Publication date: July 21, 2022
    Inventors: KUO-CHENG LU, MIN-CHANG WEI, CHUN-MING LIU, KUANG-YU YEN
  • Publication number: 20220231956
    Abstract: A data flow classification device includes a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit; but if the classification is not found in the lookup table, the forwarding circuit tags the packets with a predetermined classification, outputs the packets to the buffer circuit, and adds the information of the input flow to the lookup table. The configuring circuit determines a flow threshold according to a queue length of the buffer circuit and a target length, learns the traffic of multiple flows from the lookup table, determines the classifications of the multiple flows according to the comparison between the traffic and the flow threshold, and stores these classifications in the lookup table.
    Type: Application
    Filed: September 3, 2021
    Publication date: July 21, 2022
    Inventors: KUO-CHENG LU, MIN-CHANG WEI, CHUN-MING LIU, KUANG-YU YEN
  • Patent number: 11388115
    Abstract: The present invention provides a circuit within a switch, wherein the circuit includes a memory and a control circuit. The memory includes at least a first area and a second area, the first area is used to provide a minimum guaranteed storage space for each of a plurality of egress queues, the second area is used to provide a shared space of the plurality of egress queues. The control circuit is coupled to the memory, and when an input port of the switch receives an input packet and stores the input packet into the memory, the control circuit dynamically determines a size of the second area according to a number of the egress queues that the input packet is forwarded to.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yung-Chang Lin, Kuo-Cheng Lu
  • Publication number: 20220200925
    Abstract: Disclosed is a time-division multiplexing (TDM) scheduler capable of determining a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 23, 2022
    Inventors: KUO-CHENG LU, YU-MEI PAN, YUNG-CHANG LIN