Abstract: Examples of efficient MAC address storage are described, including methods and an apparatus. A method may involve obtaining a plurality of identifications associated with one or more applications executed on a computing apparatus, with each identification of the plurality of identifications different from one another. The method may also involve storing an identification entry representative of the plurality of identifications associated with the one or more applications. The identification entry may require an amount of memory space for storage less than an amount of memory space required to store the plurality of identifications associated with the one or more applications. The plurality of identifications may be a plurality of MAC addresses. The one or more applications may be one or more virtual machines.

Abstract: The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.

Abstract: A method for offloading packet segmentations includes the steps of retrieving a packet segmentation offloading parameter in a packet and segmenting the packet into a plurality of sub-packets by taking consideration the packet segmentation offloading parameter. A device for offloading packet segmentations includes a packet parser configured to receive a packet to be transmitted, a header buffer controller configured to retrieve a header of the packet and connected to a buffer to access the header, an extractor configured to retrieve a packet segmentation offloading parameter in the packet, and a segmentation module configured to segment the packet into a plurality of sub-packets by taking consideration the header and the packet segmentation offloading parameter.

Abstract: A flexible positioning post includes a base, a metal post and a plurality of metal elastic pieces. The base has an upper surface. The metal post has a first end and a second end opposite to each other, and the first end is connected to the upper surface of the base. Each of the metal elastic pieces has a fixed end and a free end opposite to each other. The fixed end is securely assembled at the second end of the metal post, and the free end is adjacent to the upper surface of the base and bent toward the metal post to form a bending portion. Consequently, upon receiving a foreign force, the free end of each of the metal elastic pieces is moved toward the metal post; conversely, once the foreign force is removed, the free end of each of the metal elastic pieces is moved resiliently.

Abstract: An apparatus processes a packet and determines that the packet is a processed fast path packet or a slow path packet, wherein the processed fast path packet is forwarded to a fast path forwarding queue directly or is forwarded to a fast path output queue through a packet direct memory access controller. The apparatus not only improves the packet processing performance but also guarantees the quality of service.

Abstract: A parser is used for parsing a header in a packet. The parser includes a plurality of horizontal field selectors, a plurality of comparators, and a content addressable memory (CAM) based device. Each of the horizontal field selectors is configured to select a first bit group. The comparators are coupled to the horizontal field selectors, respectively. Each of the comparators is configured to compare a first bit group selected by a corresponding horizontal field selector with a designated value to generate a comparison result. The CAM based device is configured to receive a plurality of comparison results generated from the comparators, and use the comparison results as a first input search data.

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, a traffic manager, and a processor. The ingress packet processing circuit processes an ingress packet received from an ingress port to generate at least one parameter. The egress packet processing circuit has at least one programmable look-up table, refers to the at least one parameter to determine at least one action command set, and executes the at least one action command set for generating an egress packet to be forwarded through an egress port. The traffic manager is coupled between the ingress packet processing circuit and the egress packet processing circuit. The processor programs the at least one programmable look-up table. No action command in the at least one action command set is transmitted from the ingress packet processing circuit to the egress packet processing circuit through the traffic manager.

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.

Abstract: A flexible positioning post includes a base, a metal post and a plurality of metal elastic pieces. The base has an upper surface. The metal post has a first end and a second end opposite to each other, and the first end is connected to the upper surface of the base. Each of the metal elastic pieces has a fixed end and a free end opposite to each other. The fixed end is securely assembled at the second end of the metal post, and the free end is adjacent to the upper surface of the base and bent toward the metal post to form a bending portion. Consequently, upon receiving a foreign force, the free end of each of the metal elastic pieces is moved toward the metal post; conversely, once the foreign force is removed, the free end of each of the metal elastic pieces is moved resiliently.

Abstract: A network processor for processing packet switching in a network switching system is disclosed. The network processor includes a first memory for storing a first packet among a plurality of packets; a second memory for storing a second packet among the plurality of packets; and a memory selecting unit for selecting the first memory or the second memory for storing each of the plurality of packets according to whether a traffic of the network switching system is congested; wherein attributes of the first memory and the second memory are different.

Abstract: The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU.

Abstract: A display and an electrostatic discharge protection apparatus are disclosed, wherein the display includes a display module, a flex flat cable, a motherboard, and an electrostatic discharge protection apparatus. The flex flat cable is electrically connected with the display module and the motherboard; the electrostatic discharge protection apparatus is disposed between the flex flat cable and the display module. The electrostatic discharge protection apparatus has an isolation board and at least one isolation pad, the isolation board includes a first surface and a second surface, and at least one part of the first surface is attached to the flex flat cable; the isolation pad comprises a first isolation surface, and the first isolation surface is combined with the second surface.

Abstract: A packet processing method includes receiving a forwarding decision made for an input packet; and creating a packet processing list of the input packet according to the forwarding decision. When the forwarding decision indicates that the input packet is required to undergo first packet processing operations, each including a common processing operation and an individual processing operation, to generate first output packets forwarded via first egress ports, respectively, first information indicative of the first egress ports is recorded in an egress port field of a first session of the packet processing list; second information indicative of the common processing operation shared by all of the first packet processing operations is recorded in a common processing field of the first session; and third information indicative of individual processing operations of the first packet processing operations is recorded in an individual processing field of the first session.

Abstract: A network processor for processing packet switching in a network switching system is disclosed. The network processor includes a first memory for storing a first packet among a plurality of packets; a second memory for storing a second packet among the plurality of packets; and a memory selecting unit for selecting the first memory or the second memory for storing each of the plurality of packets according to whether a traffic of the network switching system is congested; wherein attributes of the first memory and the second memory are different.

Abstract: A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system.

Abstract: A display and an electrostatic discharge protection apparatus are disclosed, wherein the display includes a display module, a flex flat cable, a motherboard, and an electrostatic discharge protection apparatus. The flex flat cable is electrically connected with the display module and the motherboard; the electrostatic discharge protection apparatus is disposed between the flex flat cable and the display module. The electrostatic discharge protection apparatus has an isolation board and at least one isolation pad, the isolation board includes a first surface and a second surface, and at least one part of the first surface is attached to the flex flat cable; the isolation pad comprises a first isolation surface, and the first isolation surface is combined with the second surface.

Abstract: The present invention discloses a communication device, including a first network interface, for receiving a plurality of packets composed of a plurality of first packets destined to a first communication device and a plurality of second packets, a first reordering engine, for reordering the plurality of first packets, outputting the plurality of reordered first packets, and outputting the plurality of second packets, a second reordering engine, for receiving the plurality of second packets from the first reordering engine, and reordering the plurality of second packets, a second network interface, for receiving the plurality of reordered first packets from the first reordering engine, and transmitting the plurality of reordered first packets to the first communication device, and a processing module, for processing the plurality of reordered second packets.

Abstract: The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU.

Abstract: A buffer space allocation method for a packet switch includes periodically performing a measurement process to obtain a plurality of measurement results at different times, each measurement result indicating a total size of accumulated packets in an output queue corresponding to one of a plurality of network ports of the packet switch, and adjusting a dedicated buffer space of the output queue according to the plurality of measurement results and a reserved space value for the dedicated buffer space.

Abstract: A quality of service (QoS) arbitration method for an on-chip bus is disclosed. The bus arbitration method includes steps of classifying each of a plurality of requestors into one of a plurality of first QoS types; classifying the each of the plurality of requestors into one of a plurality of second QoS types corresponding to a plurality of service priorities according to a due date or a data rate of the each of the plurality of requestors and the one of the plurality of first QoS types; and choosing a requestor with a highest service priority among the plurality of requestors to service.