Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

Abstract: A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.

Abstract: A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

Abstract: Disclosed is a method for manufacturing deep trench structure comprising the steps of providing a substrate; forming a deep trench in the substrate; forming a nitride layer in the deep trench; filling the deep trench with a first conductive layer; removing a portion of the nitride layer not covered by the first conductive layer; refilling the deep trench with another nitride layer so that the sidewall of the deep trench not covered by the first polymer, is covered; partially removing the refilled nitride layer; forming a collar oxide layer in the deep trench; filling the deep trench with a second conductive layer; removing a portion of the collar oxide layer not covered by the second conductive layer; and filling the deep trench with a third conductive layer.

Abstract: A method for avoiding short circuits between conductive wires. The method includes providing a substrate having a contact area, forming a first opening in the substrate to expose the contact area, filling the first opening with a first conductive material to form a first conductive layer, removing a portion of the first conductive layer to form a second opening, in order to expose a sidewall of the substrate, forming a spacer on the sidewall, depositing a poly-silicon layer over the substrate to fill the second opening to form a second conductive layer, etching back the poly-silicon layer to expose a portion of the spacer, forming a patterned dielectric layer over the substrate to define a wire opening in order to expose the second conductive layer, and filling the wire opening with a third conductive material to form a wire electrically connected with the second conductive layer.

Abstract: A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

Abstract: A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

Abstract: A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.

Abstract: A semiconductor device and method of manufacturing the same are disclosed. A conductive structure, spacers and a dielectric layer are formed on a substrate. Thereafter, a portion of the cap layer, a portion of the spacers and a portion of the dielectric layer of the conductive structure are removed to form a funnel-shaped opening. The shoulder section of the conductive layer exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed inside the funnel-shaped opening. Another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed over the substrate.

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

Abstract: This invention discloses a method for fabricating a deep trench capacitor. A substrate is provided. A pad oxide layer and a pad nitride layer are stacked on a main surface of the substrate. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A doped area is formed at the lower portion of the deep trench serving as the first electrode of the trench capacitor. A node dielectric is coated on the interior surface of the deep trench. A first polysilicon layer is deposited in the deep trench and is then recessed to a first depth. A silicon spacer layer is formed on sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The un-doped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate.

Abstract: A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

Abstract: A method for making a deep trench capacitor is disclosed. A substrate with a deep trench formed therein is provided. The trench is doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the trench. A node dielectric is formed on interior surface of the trench. Subsequently, the trench is filled with a first conductive layer and then recessed to a first depth. A collar oxide layer is then formed on vertical sidewall of the trench on the first conductive layer. The trench is filled with a second conductive layer and again recessed to a second depth. A pair of symmetric spacers is then formed on the vertical sidewall of the trench. A third conductive layer is deposited on the second conductive layer and on the symmetric spacers, and fills the trench. The trench is recessed to a third depth.

Abstract: A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.