Abstract: A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.

Abstract: A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.

Abstract: A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

Abstract: A method for forming silicide at source and drain. The method includes providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on two sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer from the peripheral region; removing the mask layer, forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process such that silicon reacts with the metal to form silicide at the source and the drain.

Abstract: A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.

Abstract: A method for forming silicide at source and drain. The method includes providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on two sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer from the peripheral region; removing the mask layer, forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process such that silicon reacts with the metal to form silicide at the source and the drain.

Abstract: A method for forming a bit line contact, which electrically couples to a contact region of a substrate, is provided. The method includes the step of forming an opening in the substrate to expose the contact region. A polysilicon layer is formed in a portion of the opening to electrically couple to the contact region. Then, ions are implanted into the polysilicon layer to transform an upper portion of the polysilicon layer to an amorphous layer. Next, a conductive layer is formed on the amorphous layer.

Abstract: A method is provided for manufacturing a polysilicon with a relatively small line width. The method includes steps of: a) forming a first layer of photoresist with a line pattern having a first line interval and a first line width over the polysilicon; b) etching a portion of the polysilicon for forming the polysilicon with a second line interval x and a second line width y respectively equal to the first line interval and the first line width; c) forming a second layer of photoresist with a third line interval and a third line width over the polysilicon; d) etching another portion of the polysilicon for forming the polysilicon with a fourth line interval x`, equal to the third line interval, and a fourth line width y`; e) depositing a polysilicon film over the polysilicon with the relatively small line width; and f) etching a portion of the polysilicon film to form sidewalls of the polysilicon with the relatively small line width for adjusting the relatively small line width of the polysilicon.