Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: The present disclosure relates to an image sensor including a first semiconductor layer having a first doping type. A second semiconductor layer having the first doping type is between sidewalls of the first semiconductor layer and extends vertically along the sidewalls of the first semiconductor layer from a bottom side of the first semiconductor layer toward a top side of the first semiconductor layer. A first doped region having the first doping type is in the first semiconductor layer and laterally beside the second semiconductor layer. The first doped region extends vertically along a sidewall of the second semiconductor layer. A second doped region having a second doping type is in the first semiconductor layer and laterally beside the first doped region. The second doped region extends vertically along a side of the first doped region and forms a p-n junction with the first doped region.

Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Abstract: The present invention discloses an antenna selection method, where the antenna selection method includes the steps of: utilizing a first vertical polarized antenna and a second vertical polarized antenna to obtain a first signal; calculating a first signal quality parameter according to the first signal; utilizing the first vertical polarized antenna and a horizontal polarized antenna to obtain a second signal; calculating a second signal quality parameter according to the second signal; and selecting one of the second vertical polarized antenna and the horizontal polarized antenna according to the first signal quality parameter and the second signal quality parameter, to be matched with the first vertical polarized antenna for subsequent signal transmission and reception.

Abstract: A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.

Abstract: The present invention discloses an antenna selection method, where the antenna selection method includes the steps of: utilizing a first vertical polarized antenna and a second vertical polarized antenna to obtain a first signal; calculating a first signal quality parameter according to the first signal; utilizing the first vertical polarized antenna and a horizontal polarized antenna to obtain a second signal; calculating a second signal quality parameter according to the second signal; and selecting one of the second vertical polarized antenna and the horizontal polarized antenna according to the first signal quality parameter and the second signal quality parameter, to be matched with the first vertical polarized antenna for subsequent signal transmission and reception.

Abstract: A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.

Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.

Abstract: A sensor device is disclosed. The sensor device include: a detector having a contact formation region; an insulating layer disposed over the detector; a conductive pad disposed over the insulating layer opposite to a side of the detector; a contact plug formed in the insulating layer for electrically coupling the contact implant region and the conductive pad; and a read-out integrated circuit bonded to the insulating layer through the conductive pad. An image sensor array and a manufacturing method of a sensor device are also disclosed.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.

Abstract: A light convergence module with a heat dissipation function is revealed. It comprises a substrate, an assembling unit, a light convergence lampshade, and a heat sink, wherein the assembling unit with a first surface assembling to the substrate and a second surface assembling to the light convergence lampshade comprises a locating block and a plurality of position limiting blocks for respectively engaging with a locating slot and a plurality of position limiting slots of the substrate, and two buckles for correspondingly clasping two concave slots of the substrate to limit the substrate in position, and wherein the heat sink comprises a plurality of interspaces formed between every two adjacent heat dissipation fins for securing the buckles of the assembling unit and allowing the heat sink to closely dispose on the substrate.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.