Patents by Inventor Kuo-Chun Hsu

Kuo-Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7578701
    Abstract: An electrical connector (100) includes an insulating housing having a pair of longitudinal side walls (11) and a pair of end walls (12) connecting the side walls thereby defining a receiving cavity therebetween. A plurality of terminal grooves (13) are defined in an inner side of the side wall and exposed to the receiving cavity. A plurality of terminals are received in said terminal grooves and comprise signal terminals and grounding terminals. At least one shell (3) covers on an outer side of the side wall and defines an upper side and a lower side. At least one grounding arm (33) is formed at the lower side of the shell and spaced to the lower side of the shell thereby forming a slot (333) therebetween. The at least one grounding arm (33) has a first portion (331) abutting against the side wall and a second portion (332) mechanically and electrically contacting with the grounding terminal.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: August 25, 2009
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Kuo-Chun Hsu
  • Patent number: 7540762
    Abstract: An electrical connector (100) includes an insulating housing (10) defining a receiving space (12) for receiving a sheet-like connection member. A plurality of conductive terminals (20) each defines a contacting portion (241, 251) projecting to the receiving space. A slider (40) includes a tongue portion (43) to be movable inserted into the receiving space (12) and urging the sheet-like connection member to engage with the contacting portions. The tongue portion has a first portion (431) and a second portion (43) in an inserting direction thereof, and the second portion (43) is shorter than the first portion (431) in a longitudinal direction perpendicular to the inserting direction.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 2, 2009
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Min-Han Lin, Kuo-Chun Hsu
  • Publication number: 20090047833
    Abstract: An electrical connector for connecting an FPC includes an insulating housing having a receiving space, a plurality of contacts received in the insulating housing and an actuator retained on two ends of said insulating housing. Each contact includes a pivot arm engaging with said actuator and frontwardly extending into said receiving space. Said pivot arm defines a first engaging notch and a protrusion on a bottom edge thereof. The actuator has a rotatable cam portion rotatablely engaged with said first engaging notch. Said protrusion is formed on a frontal tip end of said pivot arm and extends much lower than said rotatable cam portion in a vertical direction, which prevents the FPC from contacting with said rotatable portion firstly during the process of the insertion.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 19, 2009
    Inventors: Min-Han Lin, Kuo-Chun Hsu
  • Publication number: 20090011651
    Abstract: An electrical connector includes an insulating housing defining a receiving cavity for receiving an FPC, a pressing member assembled on the insulating housing, a plurality of contacts received in the insulating housing and a pair of locking members retained on two ends of the insulating housing. The pressing member has a tongue plate inserted into the receiving cavity for urging the FPC. The tongue plate has a pair of standoff portions with a pair of depressed recesses thereon in order to engage with the locking members.
    Type: Application
    Filed: June 30, 2008
    Publication date: January 8, 2009
    Inventors: Min-Han Lin, Kuo-Chun Hsu
  • Publication number: 20090009916
    Abstract: An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
    Type: Application
    Filed: May 2, 2008
    Publication date: January 8, 2009
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu, Hsin-Chin Jiang
  • Publication number: 20080318466
    Abstract: An electrical connector (100) includes an insulating housing (10) defining a receiving space (12) for receiving a sheet-like connection member. A plurality of conductive terminals (20) each defines a contacting portion (241, 251) projecting to the receiving space. A slider (40) includes a tongue portion (43) to be movable inserted into the receiving space (12) and urging the sheet-like connection member to engage with the contacting portions. The tongue portion has a first portion (431) and a second portion (43) in an inserting direction thereof, and the second portion (43) is shorter than the first portion (431) in a longitudinal direction perpendicular to the inserting direction.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 25, 2008
    Inventors: Min-Han Lin, Kuo-Chun Hsu
  • Patent number: 7436041
    Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 14, 2008
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Patent number: 7402088
    Abstract: An electrical connector for connecting a sheet-like connection member (6) with a plurality of conductive pads (60) thereon comprises an insulative housing (1) defining a receiving cavity (10), and a plurality of conductive terminals (2) arranged in the insulative housing. Each terminal is made by stamping a piece of metal plate and comprises a base section (20), a first resilient arm (21) extending aslant from the base section, an extending section extending forwards from the base section and a second resilient arm (23) extending aslant from said extending section. The first and the second resilient arms (21,23) of each terminal respectively has a contact portion (211,231) to electrically and mechanically contact with a corresponding same conductive pad (60) of said sheet-like connection member (6).
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: July 22, 2008
    Assignee: Hon Hai Precision Ind. Co., Ltd
    Inventors: Kuo-Chun Hsu, Ti-Li Wei
  • Publication number: 20080157831
    Abstract: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventor: Kuo-Chun Hsu
  • Patent number: 7394630
    Abstract: An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: July 1, 2008
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu, Hsin-Chin Jiang
  • Publication number: 20080054297
    Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Application
    Filed: December 20, 2005
    Publication date: March 6, 2008
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Publication number: 20080038957
    Abstract: An electrical connector for connecting a sheet-like connection member (6) with a plurality of conductive pads (60) thereon comprises an insulative housing (1) defining a receiving cavity (10), and a plurality of conductive terminals (2) arranged in the insulative housing. Each terminal is made by stamping a piece of metal plate and comprises a base section (20), a first resilient arm (21) extending aslant from the base section, an extending section extending forwards from the base section and a second resilient arm (23) extending aslant from said extending section. The first and the second resilient arms (21,23) of each terminal respectively has a contact portion (211,231) to electrically and mechanically contact with a corresponding same conductive pad (60) of said sheet-like connection member (6).
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Inventors: Kuo-Chun Hsu, Ti-Li Wei
  • Publication number: 20080038952
    Abstract: An electrical connector for connecting a sheet-like connection member includes an insulating housing (1) with a receiving cavity (10) and a supporting portion (16) on a first end thereof, a plurality of terminals (2) arranged in the insulative housing (1) and a stuffer (3) comprising a tongue plate (31) insertable to the receiving cavity (10) and a pivot portion (32) defined at one end thereof. The pivot portion (32) is assembled on the supporting portion (16) of the insulative housing and the stuffer (3) rotates about the pivot portion (32).
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Inventors: Kuo-Chun Hsu, Ti-Li Wei
  • Publication number: 20070103210
    Abstract: A power-on reset circuit for an integrated circuit has a trigger unit that includes (i) a first voltage drop element with a first terminal for coupling to a supply voltage, and a second terminal; (ii) a second voltage drop element with a first terminal, coupled to the second terminal of the first voltage drop element, and a second terminal; and (iii) an inverter with an input, coupled to the first terminal of the second voltage drop element, and an output. A discharge unit is provided to conduct a current from the trigger unit during a decrease of the supply voltage to decrease the voltage at the input of the first inverter, and substantially block current from the trigger unit during an increase of the supply voltage.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 10, 2007
    Inventor: Kuo-Chun Hsu
  • Patent number: 7071528
    Abstract: A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 4, 2006
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Patent number: 6954098
    Abstract: A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 11, 2005
    Assignee: ADMtek Incorporated
    Inventors: Kuo-Chun Hsu, Ming-Dou Ker
  • Publication number: 20050200396
    Abstract: A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.
    Type: Application
    Filed: April 30, 2004
    Publication date: September 15, 2005
    Inventors: Kuo-Chun Hsu, Ming-Dou Ker
  • Publication number: 20050133869
    Abstract: A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Application
    Filed: April 28, 2004
    Publication date: June 23, 2005
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Patent number: 6858901
    Abstract: An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger drain coupled to a pad, a plurality of voltage drop elements, each of which is coupled between one of the finger sources and a power line to detect a transient current flowing through one of the finger gates, and a plurality of feedback circuits, each of which is coupled between a base and an emitter respectively of a first and second parasitic BJT, and activates the first BJT to bypass ESD current during an ESD event.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • Patent number: 6744107
    Abstract: An electrostatic discharge protection circuit. The electrostatic discharge protection circuit utilizes the non-uniform triggering of multi-finger gate-grounded NMOS. The source of the finger which has the potential to trigger on is coupled to the base terminal of all the parasitic bipolar transistor of all the other multi-finger gate-ground NMOS structures. Thus, the finger which has the potential to be triggered can be used as a triggering device to trigger the other finger devices during an ESD event. By using this method, the ESD protection NMOS or PMOS, realized with multi-finger layout structure, can be uniformally triggered on to discharge ESD current. Therefore, it can have a high ESD robustness in a small layout area.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: June 1, 2004
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu, Wen-Yu Lo