Abstract: The present disclosure provides a bolometer including a substrate, a reflecting mirror on the substrate, and a temperature sensing unit above the reflecting mirror. The temperature sensing unit includes a first insulating layer, a thermistor on the first insulating layer, a second insulating layer on the thermistor, an electrode layer in the second insulating layer and right above the thermistor, and a metal meta-surface in the second insulating layer and right above the electrode layer. The electrode layer includes a plurality of electrodes separated from each other. A projection region of the metal meta-surface on the thermistor is equal to or larger than the thermistor.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.

Abstract: A transformer includes a magnetic core assembly, a bobbin, two first windings, a second winding and a second circuit board. A bobbin channel runs through two opposite sides of the bobbin main body. The winding portion is formed on an outer periphery surface of the bobbin main body. The two first windings are disposed around the winding portion. One of the two first windings is disposed between the other one of the two first windings and the outer periphery surface of the bobbin main body. The second winding is disposed around the winding portion and disposed between the two first windings. The second circuit board hole and the bobbin channel are in communication with each other. The magnetic core assembly partially penetrates through the bobbin channel and the second circuit board hole. The second winding and the second circuit board are connected with each other in parallel.

Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.

Abstract: A transformer includes a magnetic core assembly, a bobbin, two first windings, a second winding and at least one circuit board. The bobbin includes a bobbin main body, a bobbin channel and a winding portion. The winding portion is formed on an outer periphery surface of the bobbin main body. The two first windings are disposed around the winding portion. One of the two first windings is disposed between the other one of the two first windings and the outer periphery surface of the bobbin main body. The second winding is disposed around the winding portion and disposed between the two first windings. The at least one circuit board includes a circuit board hole. The circuit board hole and the bobbin channel are communicated with each other. The magnetic core assembly partially penetrates through the circuit board hole and the bobbin channel.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: A method of removing sludge from a drain pipe used for cleaning a drain pipe comprises a piling step, a platform setting step, a drilling path planning step, a coil deploying step, a conveying bracket lifting step, a guiding step, a drilling step, and a cleaning step. In the piling step, a plurality of supporting columns are provided around the opening of the drain pipe. In the platform setting step, a work platform is provided on the plurality of supporting columns. In the drilling path planning step, a drilling path is planned. In the coil deploying step, an induction coil group is placed above the drain pipe. In the conveying bracket lifting step, a conveying bracket is hung by lifting equipment so that the conveying bracket is aligned with the opening of the drain pipe. In the guiding step, the drill bit is guided to the opening of the drain pipe using the conveying bracket. In the drilling step, the drill bit is controlled to drill into the clogged bulk in the drain pipe.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

Abstract: In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: A semiconductor package and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a substrate and transistors formed at a front side of the substrate; a power distribution network, spreading at a back side of the substrate and penetrating through the substrate, to provide power and ground signals to the transistors; a dielectric material, laterally surrounding the first semiconductor die; and a second semiconductor die, having a central portion bonded with the first semiconductor die and a peripheral portion in contact with the dielectric material.

Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, an edge detector and a trigger device. The transfer chamber is configured to interface with an electroplating apparatus. The robot arm is arranged to transfer a wafer from the transfer chamber to the annealing station. The edge detector, disposed over a predetermined location between the transfer chamber and the annealing station, comprises a first charge-coupled device (CCD) sensor and a second CCD sensor. When the robot arm is carrying the wafer to pass through the predetermined location, the first CCD sensor and the second CCD sensor are located over a first portion and a second portion of the edge bevel removal area respectively, and the trigger device is configured to activate the first CCD sensor and the second CCD sensor to capture an image of the first portion and an image of the second portion respectively.

Abstract: A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.

Abstract: A semiconductor die, a semiconductor package and manufacturing methods thereof are provided. The semiconductor die includes: a front-end-of-line (FEOL) structure, built on a semiconductor substrate; a back-end-of-line (BEOL) structure, formed on the FEOL structure, and including a stack of metallization layers; and bonding metals, disposed on the BEOL structure. The bonding metals include: a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure; a conductive capping layer, lining along a top surface of the conductive pad; and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer. The semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.