Patents by Inventor Kuo H. Wu

Kuo H. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304942
    Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyun-Ming Lin, Hua Feng Chen, Kuo-Hua Pan, Min-Yann Hsieh, C. H. Wu
  • Patent number: 9559003
    Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Publication number: 20150357240
    Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 9111936
    Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 9099540
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 9026475
    Abstract: A method for manufacturing integrated circuits (“ICs”) is disclosed. The method pertains to providing third-party technology in the form of an IC design library to foundry customers for designing IC products using alternate rule sets. Aggressive rules pertaining to IC layout are used to reduce device size, resulting in more device per wafer for the customer. The method includes a library creator creating a slim cell library, a slim cell library being provided to a customer to enable the customer to generate a slim IC design; an IC fabricator charging the customer a per-wafer premium to fabricate the slim IC design; the IC fabricator providing a first portion of the premium to a first entity, wherein the first entity is a contributor of technology for enabling creation of the slim cell library; and the IC fabricator providing a second portion of the premium to the library creator.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo H. Wu
  • Publication number: 20140264941
    Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8753939
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8674510
    Abstract: A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Publication number: 20130316530
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: November 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M.K. Law, Kuo H. Wu
  • Patent number: 8589847
    Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8552563
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8549460
    Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu, Wei-Chih Yeh
  • Patent number: 8487444
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8332794
    Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8314635
    Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Publication number: 20120290996
    Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu, Wei-Chih Yeh
  • Patent number: 8264067
    Abstract: A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu, Wei-Chih Yeh
  • Patent number: 8247906
    Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: August 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu, Wei-Chih Yeh
  • Patent number: 8136067
    Abstract: Disclosed is a system and method for enhancing integrated circuit designs and predicting the manufacturability. Design for manufacturability, or DFM, is an integration of DFM advisories; a DFM data kit presented in a DFM unified format; and DFM utilities utilizing the DFM data kit and the DFM advisories for enhancing integrated circuit (IC) designing.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: March 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo H. Wu