Patents by Inventor Kuo Han
Kuo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Patent number: 11973027Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.Type: GrantFiled: March 23, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
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Patent number: 11964915Abstract: A ceramic material includes zirconia toughened alumina (ZTA), which is doped with zinc ions and other metal ions, in which the other metal ions are chromium (Cr) ions, titanium (Ti) ions, gadolinium (Gd) ions, manganese (Mn) ions, cobalt (Co) ions, iron (Fe) ions, or a combination thereof. The ceramic material may have a hardness of 1600 Hv10 to 2200 Hv10 and a bending strength of 600 MPa to 645 MPa. The ceramic material can be used as wire bonding capillary.Type: GrantFiled: December 17, 2021Date of Patent: April 23, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tien-Heng Huang, Yu-Han Wu, Kuo-Chuang Chiu
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Publication number: 20240128324Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.Type: ApplicationFiled: November 21, 2022Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
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Publication number: 20240130055Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Cheng HUANG, I-Hung CHIANG, Ji-Yuan SYU, Hsin-Han LIN, Po-Kai CHIU, Kuo-Shu KAO
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Publication number: 20240120277Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
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Patent number: 11955444Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.Type: GrantFiled: October 13, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Manikandan Arumugam, Tsung-Yi Yang, Chien-Chih Chen, Mu-Han Cheng, Kuo-Hsien Cheng
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Publication number: 20240096882Abstract: A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Han LIU, Chih-Hao WANG, Kuo-Cheng CHIANG, Shi-Ning JU, Kuan-Lun CHENG
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Publication number: 20240092665Abstract: A method for treating wastewater containing ertriazole compounds is provided. Hypochlorous acid (HOCl) having a neutral to slightly acidic pH value is added to the wastewater containing triazole compounds for reaction, thereby effectively reacting more than 90% of triazole compounds.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: KUO-CHING LIN, YUNG-CHENG CHIANG, SHR-HAN SHIU, MENG-CHIH CHUNG, YI-SYUAN HUANG
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Publication number: 20240083758Abstract: Embodiments of the present disclosure relate to zeolites and method for making such zeolites. According to embodiments disclosed herein, a zeolite may have a microporous framework including a plurality of micropores having diameters of less than or equal to 2 nm and a plurality of mesopores having diameters of greater than 2 nm and less than or equal to 50 nm. The microporous framework may include an MFI framework type. The microporous framework may include silicon atoms, aluminum atoms, oxygen atoms, and transition metal atoms. The transition metal atoms may be dispersed throughout the entire microporous framework.Type: ApplicationFiled: October 25, 2023Publication date: March 14, 2024Applicants: Saudi Arabian Oil Company, King Abdullah University of Science and TechnologyInventors: Robert Peter Hodgkins, Omer Refa Koseoglu, Kuo-Wei Huang, Jean-Marie Maurice Basset, Yu Han, Rajesh Parsapur, Anissa Bendjeriou Sedjerari, Sathiyamoorthy Murugesan
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Publication number: 20240072074Abstract: Please replace the abstract originally filed with the following: A display panel and a display device. Because the pixel distribution density in a second display subarea (A12) is lower than that in a first display subarea (A11), the quantities of sub-pixels (pix) connected to scanning lines are not completely the same; a sub-pixel row having the greatest quantity of sub-pixels (pix) in the display panel is taken as a reference sub-pixel row, the quantity of the sub-pixels (pix) of the reference sub-pixel row is taken as a reference value, a sub-pixel row having the quantity of sub-pixels (pix) smaller than the reference value is taken as a compensation sub-pixel row, and a scanning line connected to the compensation sub-pixel row is taken as a first scanning line; the display panel is provided with load compensation units corresponding to at least part of the first scanning lines, and the load compensation units are located in the second display subarea.Type: ApplicationFiled: March 9, 2021Publication date: February 29, 2024Inventors: Wenqiang LI, Long HAN, SHI Ling, Ke LIU, Xuewei TIAN, Kuo SUN, Pinfan WANG
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Patent number: 11776867Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.Type: GrantFiled: June 14, 2022Date of Patent: October 3, 2023Assignee: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
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Patent number: 11756858Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.Type: GrantFiled: January 4, 2021Date of Patent: September 12, 2023Assignees: Industrial Technology Research Institute, DIODES TAIWAN S.A R.L.Inventors: Wei-Kuo Han, Chia-Yen Lee, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 11648649Abstract: The tool connector includes a socket having a receiving space and a through hole communicating the receiving space, a sliding member slidably received in the receiving space, a positioning member received in the receiving space, and a hook member. A funnel-shaped opening is formed at an end of the receiving space. The sliding member is connected to the socket with an end via a first elastic member, and the other end is for a tool bit to abut against. The positioning member is selectively inserted into the through hole. An end of the hook member is connected to the sliding member, and the other end has a hook portion for grasp the tool bit. When the positioning member is moved inward and the sliding member is moved toward the funnel-shaped opening, the hook portion is swingable in the funnel-shaped opening to release the tool bit.Type: GrantFiled: June 18, 2021Date of Patent: May 16, 2023Inventor: Kuo-Han Liu
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Publication number: 20220310473Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.Type: ApplicationFiled: June 14, 2022Publication date: September 29, 2022Applicant: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
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Patent number: 11387159Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.Type: GrantFiled: March 4, 2020Date of Patent: July 12, 2022Assignee: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
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Publication number: 20220080566Abstract: The tool connector includes a socket having a receiving space and a through hole communicating the receiving space, a sliding member slidably received in the receiving space, a positioning member received in the receiving space, and a hook member. A funnel-shaped opening is formed at an end of the receiving space. The sliding member is connected to the socket with an end via a first elastic member, and the other end is for a tool bit to abut against. The positioning member is selectively inserted into the through hole. An end of the hook member is connected to the sliding member, and the other end has a hook portion for grasp the tool bit. When the positioning member is moved inward and the sliding member is moved toward the funnel-shaped opening, the hook portion is swingable in the funnel-shaped opening to release the tool bit.Type: ApplicationFiled: June 18, 2021Publication date: March 17, 2022Inventor: Kuo-Han Liu
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Patent number: 11239211Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.Type: GrantFiled: January 7, 2020Date of Patent: February 1, 2022Assignee: Industrial Technology Research InstituteInventors: Wei-Kuo Han, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 11114387Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.Type: GrantFiled: August 22, 2018Date of Patent: September 7, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao