Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.

Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.

Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.

Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.

Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.

Abstract: A method and an apparatus for forming a cleaning a chemical vapor deposition (CVD) chamber are provided. The method includes providing a chemical vapor deposition (CVD) chamber. The method further includes introducing a remote plasma source into the CVD chamber. The method also includes performing a plasma cleaning process to the CVD chamber by applying a radio-frequency (RF) power in the CVD chamber.

Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.

Abstract: A method for driving a movable component of a hardware device to move a driving distance includes the steps of: (1) adjusting at least one of the former time and the latter time according to an advancing time so that a sum of the former time and the latter time is substantially equal to the advancing time; and (2) driving the movable component to the driving distance by the former force for the former time and by the latter force for the latter time.

Abstract: A deposition ring comprises a ring body, a groove and a protrusion structure. The ring body is planar-ring shaped, and comprises a first surface. The groove and the protrusion structure are ring shaped and formed on the first surface. The protrusion structure is close to the groove and near an outer side of the ring body. The groove comprises a first side wall, a second side wall and a bottom. A curvature radius of the first side wall is larger than a curvature radius of the second side wall. The second side wall is a continuous ring shaped wall. The bottom is formed between the first side wall and the second side wall.

Abstract: A method for driving a movable component of a hardware device includes the steps of: (1) driving the movable component to move the driving distance by the former force to determine a base time; (2) setting a reference time, wherein the reference time is smaller than the base time; (3) determining a former period according to the reference time, and determining the former distance and the latter distance according to the former time, the former force and the base time; and (4) determining a latter period according to the latter force and the latter distance, wherein the movable component is driven by the former force for the former period and then is driven by the latter force for the latter period.

Abstract: A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon.

Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.

Abstract: A method for driving a movable component of a hardware device includes the steps of: (1) driving the movable component to move the driving distance by the former force to determine a base time; (2) setting a reference time, wherein the reference time is smaller than the base time; (3) determining a former period according to the reference time, and determining the former distance and the latter distance according to the former time, the former force and the base time; and (4) determining a latter period according to the latter force and the latter distance, wherein the movable component is driven by the former force for the former period and then is driven by the latter force for the latter period.

Abstract: The invention is to provide a method for determining a maximum storage capacity of an optical information record medium having a pregroove on which predetermined address codes are marked. The method is performed by detecting the last physical predetermined address code of the predetermined address codes. The maximum storage capacity is represented in terms of time by a time value representative of the detected last physical predetermined address code.

Abstract: Faults occurring in the operation of a rapid thermal process system are detected and dynamically controlled in-situ. A data set is generated which represents the power applied to heating elements which are spatially arranged in a plurality of zones. The data is converted to a sequence of fractions respectively representing the power applied to each zone relative to the total applied power. The fractions are sequentially arranged and a least squares straight line fit for the fractions is calculated. The slope of the calculated straight line fit is used in a statistical process control system to determine whether a fault has occurred, and to make appropriate corrections in process control parameters, such as the length of time the process is carried out.

Abstract: A method is provided to prevent the forming of a high de-focusing ledge or step on the back side of a substrate or a semiconductor wafer in order to improve the photolithographic process steps in semiconductor manufacturing. In semiconductor manufacturing, various processes are performed to form various dielectric and metal layers on the front side of wafers. However, some of these materials deposit on the back side of the wafer as well. These unwanted deposits result in contaminants that break off from the back side, causing reliability problems. Those that do stay on, on the other hand, cause irregular topology, thus affecting the focusing of stepper equipment during photolithographic processes. It is disclosed in the present invention a method of forming an oxide layer which prevents the forming of such de-focusing steps on the back side of a wafer.

Abstract: In a CVD vacuum chamber processing system for depositing a blanket of refractory material, such as tungsten, upon a frontside of a semiconductor wafer, an inert gas, such as argon is directed to the backside of the wafer in a manner so as to prevent the chamber reaction gases from reacting with polysilicon or other materials on the backside of the wafer as well as to prevent the deposition of the blanket material on the backside of the wafer. This method alleviates the problems of particulate generation and loss of wafer backside datum surface due to the inadvertent buildup of unwanted materials. The wafer is placed on a heater platen and is secured by a specified range of vacuum pressures. The wafer is exposed to specified ranges of chamber pressure during the deposition phase. During the purge phase, the chamber pressure is reduced and the wafer chucking pressure is increased to a specified range. The method is terminated with the equalization of pressure between the front and backside of the wafer.

Abstract: A process for fabricating a tungsten plug, in a deep, small diameter opening, featuring a novel adhesive-barrier composite layer, located along the sides of the deep, small diameter opening, has been developed. The process features the use of a first titanium nitride barrier layer, deposited on an underlying titanium adhesive layer, via chemical vapor deposition procedures, used to enhance the conformality properties of the first titanium nitride barrier layer. A second titanium nitride barrier layer is then deposited, via plasma vapor deposition procedures, protecting the underlying CVD titanium nitride layer from the environment, while providing an improved surface for subsequent nucleation of a CVD tungsten layer.

Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer.