Abstract: A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment is performed after polycide patterning, and prior to a silicon oxide deposition, offering protection to the exposed top surface of tungsten silicide, during the silicon oxide deposition.

Abstract: A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a RTCVD procedure, featuring loading of wafers, as well as evacuation procedures, both performed at room temperature, in a first RTCVD chamber, followed by the deposition of polysilicon and tungsten silicide layers, performed in the same RTCVD chamber. The in situ, room temperature load and evacuation processes, followed by polysilicon and tungsten depositions, results in polycide interfaces with minimal levels of native oxide, thus improving device characteristics, and SRAM performance.