Patents by Inventor Kuo-Hua Chen

Kuo-Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125911
    Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Kuo-Hua CHEN, Cheng Yuan CHEN
  • Publication number: 20210116625
    Abstract: A light-emitting module structure includes a substrate, a plurality of light-emitting diodes (LEDs) disposed on the substrate, and a light-guiding layer covering the light-emitting diodes. The light-guiding layer has an upper surface, the upper surface has a plurality of recesses, and the recesses are above the light-emitting diodes or between the light-emitting diodes. This light-emitting module structure can improve the brightness and uniformity of the light-emitting module.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Pei-Song CAI, Lung-Kuan LAI, Shih-Yu YEH, Guan-Zhi CHEN, Hong-Zhi LIU, Kuo-Yen CHANG, Ching-Hua LI
  • Publication number: 20200243427
    Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
  • Patent number: 10707157
    Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
  • Patent number: 10625665
    Abstract: A flasher relay for driving a left turn signal lamp and a right turn signal lamp of a vehicle to flash includes a main body and a control circuit. The main body includes a base, a casing, and a circuit board. The circuit board is disposed on the base. The casing is mounted on the base and covers the circuit board. The control circuit is disposed on the circuit board. The control circuit includes a microchip having an input terminal coupled to a field-effect transistor and an electromagnetic buzzer. A drain of the field-effect transistor and one end of the electromagnetic buzzer are coupled to a node B. A heat dissipation terminal of the field-effect transistor is coupled to the node B, and the node B guides thermal energy to a wire.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 21, 2020
    Inventor: Kuo-Hua Chen
  • Patent number: 10347214
    Abstract: A display matrix, a display device and an associated display method are provided. The display matrix includes a first display device and a second display device. The first display device transmits a source image at a first transmitting time point. The second display device is serially connected to the first display device via a daisy chain. The first display device and the second display device are arranged in a matrix. The second display device receives the source image via the daisy chain at a second receiving time point. The first display device displays the source image at a first display time point. The first display time point is the same as or later than the second receiving time point.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 9, 2019
    Assignee: WISTRON CORPORATION
    Inventors: Pi-Chang Chiu, Kuo-Hua Chen
  • Publication number: 20170365543
    Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 21, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
  • Patent number: 9837932
    Abstract: An embodiment of the disclosure provides an electronic device including a power supply, an optical to electrical converter and a controller. The power supply outputs a first electric power. The optical to electrical converter receives an infrared light beam and converts the infrared light beam to a second electric power. The controller is coupled to the power supply and the optical to electrical converter. The controller operates in a first mode and a second mode. When the controller operates in the first mode, the controller is activated by the second electric power and after the controller is activated, the controller operates in the second mode and drives the power supply. Then, the controller receives the first electric power and stops receiving the first electric power for operation.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 5, 2017
    Assignee: WISTRON CORP.
    Inventors: Chih-Ming Hsu, Kuo-Hua Chen
  • Patent number: 9748196
    Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 29, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Kuo-Hua Chen
  • Patent number: 9589871
    Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: March 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Chin-Li Kao, Kuo-Hua Chen, Ming-Hung Chen, Dao-Long Chen
  • Patent number: 9578737
    Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 21, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo-Hua Chen, Ming-Chiang Lee, Tsung-Hsun Lee, Chen-Chuan Fan
  • Patent number: 9564393
    Abstract: A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Yi Huang, Kuo-Hua Chen, Chi-Tsung Chiu
  • Publication number: 20160300782
    Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Inventors: Tang-Yuan CHEN, Chin-Li KAO, Kuo-Hua CHEN, Ming-Hung CHEN, Dao-Long CHEN
  • Publication number: 20160170109
    Abstract: A display module includes a display panel and a reflective optical film. The display panel has a display surface. The reflective optical film is disposed on the display surface of the display panel. The reflective optical film includes a cholesteric liquid crystal layer and a first anti-glare layer. The first anti-glare layer is disposed between the display panel and the cholesteric liquid crystal layer.
    Type: Application
    Filed: October 8, 2015
    Publication date: June 16, 2016
    Inventors: Chih-Ming HSU, Kuo-Hua CHEN, Pao-Ju HSIEH, Mei-Chih PENG
  • Publication number: 20160104455
    Abstract: A display matrix, a display device and an associated display method are provided. The display matrix includes a first display device and a second display device. The first display device transmits a source image at a first transmitting time point. The second display device is serially connected to the first display device via a daisy chain. The first display device and the second display device are arranged in a matrix. The second display device receives the source image via the daisy chain at a second receiving time point. The first display device displays the source image at a first display time point. The first display time point is the same as or later than the second receiving time point.
    Type: Application
    Filed: April 13, 2015
    Publication date: April 14, 2016
    Inventors: Pi-Chang Chiu, Kuo-Hua Chen
  • Publication number: 20160079157
    Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Jen-Kuang FANG, Kuo-Hua CHEN
  • Patent number: 9271078
    Abstract: An audio output device includes a housing, a speaker, a switching unit, a fixing component and a control unit. An opening is formed on the housing. The speaker is for outputting sound. The switching unit is installed inside the housing. The fixing component is fixed in the opening of the housing for triggering the switching unit so that the switching unit outputs a switching signal. The control unit is electrically connected to the switching unit and the speaker, and the control unit controls the speaker to output sound in a corresponding sound field as the control unit receives the switching signal.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: February 23, 2016
    Assignee: Wistron Corporation
    Inventors: Chih-Ming Hsu, Kuo-Hua Chen
  • Patent number: 9196595
    Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Tzu-Hua Lin, Kuan-Neng Chen, Yan-Pin Huang
  • Patent number: 9173583
    Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion, a plurality of microprobes and at least one conductive via. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The through silicon via is disposed in the base and electrically connects the integrated circuit portion and the microprobes. Each of the microprobes includes an isolation layer partially covering a conductive layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 3, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Chih-Wei Chang, Jin-Chern Chiou
  • Patent number: 9089268
    Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion and a plurality of microprobes. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The conductive vias are disposed in the microprobes and electrically connected to the integrated circuit portion.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 28, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Kuo-Hua Chen