Patents by Inventor Kuo-Hua Chen
Kuo-Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240149740Abstract: A public transport vehicle charging system is applied to multiple charging stations and an electric vehicle. The public transport vehicle charging system includes a server communicatively connected to the charging stations and the electric vehicle. The server is configured to establish a charging decision model according to multiple historical conditions and a transport schedule. The server is configured to calculate multiple ideal decisions according to the historical conditions and the transport schedule, so as to adjust multiple parameters in the charging decision model. When the electric vehicle drives toward a first charging station according to the transport schedule, the server is configured to input a current condition into the charging decision model, so as to selectively charge the electric vehicle by the first charging station. The current condition includes a current remaining power and a current position of the electric vehicle.Type: ApplicationFiled: November 21, 2022Publication date: May 9, 2024Inventors: Yweting TSAI, Shih-I CHEN, Kuo-Hua WU, Yu-Jin LIN, Hong-Tzer YANG
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Patent number: 11935950Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: GrantFiled: August 23, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 11923413Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.Type: GrantFiled: February 7, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
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Publication number: 20240066996Abstract: A battery system for an electric vehicle is provided. The electric vehicle includes a motor and a vehicle control unit. The battery system includes a first battery module, a second battery module configured to accommodate a plurality of swappable batteries, and a power control module configured to receive a driving intention from the vehicle control unit and switch a power supplying configuration of the motor according to the driving intention. The power supplying configuration includes a power supply by the first battery module only, a power supply by the second battery module only, a power supply by the first battery module and the second battery module in series, and a power supply by the first battery module and the second battery module in parallel.Type: ApplicationFiled: August 23, 2023Publication date: February 29, 2024Applicant: MIH CONSORTIUMInventor: KUO-HUA CHEN
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Publication number: 20240072155Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
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Publication number: 20240067045Abstract: A battery system for electric vehicles is provided. The battery system includes a first battery module, a second battery module configured to accommodate multiple swappable batteries and a switch device. The switch device is configured to switch a first connection configuration between the first battery module and the second battery module, and to switch a second connection configuration between the swappable batteries when switching the first connection configuration. Each of the first connection configuration and the second connection configuration includes a series connection and a parallel connection. In addition, a power control system and a control method of the battery system are also provided.Type: ApplicationFiled: August 23, 2023Publication date: February 29, 2024Inventor: KUO-HUA CHEN
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Patent number: 11728252Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: GrantFiled: April 10, 2020Date of Patent: August 15, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
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Patent number: 11133245Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.Type: GrantFiled: October 25, 2019Date of Patent: September 28, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Tsung Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Cheng Yuan Chen
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Publication number: 20210125911Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Kuo-Hua CHEN, Cheng Yuan CHEN
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Publication number: 20200243427Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
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Patent number: 10707157Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: GrantFiled: June 13, 2017Date of Patent: July 7, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
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Patent number: 10625665Abstract: A flasher relay for driving a left turn signal lamp and a right turn signal lamp of a vehicle to flash includes a main body and a control circuit. The main body includes a base, a casing, and a circuit board. The circuit board is disposed on the base. The casing is mounted on the base and covers the circuit board. The control circuit is disposed on the circuit board. The control circuit includes a microchip having an input terminal coupled to a field-effect transistor and an electromagnetic buzzer. A drain of the field-effect transistor and one end of the electromagnetic buzzer are coupled to a node B. A heat dissipation terminal of the field-effect transistor is coupled to the node B, and the node B guides thermal energy to a wire.Type: GrantFiled: May 29, 2019Date of Patent: April 21, 2020Inventor: Kuo-Hua Chen
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Patent number: 10347214Abstract: A display matrix, a display device and an associated display method are provided. The display matrix includes a first display device and a second display device. The first display device transmits a source image at a first transmitting time point. The second display device is serially connected to the first display device via a daisy chain. The first display device and the second display device are arranged in a matrix. The second display device receives the source image via the daisy chain at a second receiving time point. The first display device displays the source image at a first display time point. The first display time point is the same as or later than the second receiving time point.Type: GrantFiled: April 13, 2015Date of Patent: July 9, 2019Assignee: WISTRON CORPORATIONInventors: Pi-Chang Chiu, Kuo-Hua Chen
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Publication number: 20170365543Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: ApplicationFiled: June 13, 2017Publication date: December 21, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
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Patent number: 9837932Abstract: An embodiment of the disclosure provides an electronic device including a power supply, an optical to electrical converter and a controller. The power supply outputs a first electric power. The optical to electrical converter receives an infrared light beam and converts the infrared light beam to a second electric power. The controller is coupled to the power supply and the optical to electrical converter. The controller operates in a first mode and a second mode. When the controller operates in the first mode, the controller is activated by the second electric power and after the controller is activated, the controller operates in the second mode and drives the power supply. Then, the controller receives the first electric power and stops receiving the first electric power for operation.Type: GrantFiled: July 29, 2013Date of Patent: December 5, 2017Assignee: WISTRON CORP.Inventors: Chih-Ming Hsu, Kuo-Hua Chen
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Patent number: 9748196Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.Type: GrantFiled: September 15, 2014Date of Patent: August 29, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jen-Kuang Fang, Kuo-Hua Chen
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Patent number: 9589871Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.Type: GrantFiled: April 13, 2015Date of Patent: March 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tang-Yuan Chen, Chin-Li Kao, Kuo-Hua Chen, Ming-Hung Chen, Dao-Long Chen
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Patent number: 9578737Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.Type: GrantFiled: January 31, 2014Date of Patent: February 21, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuo-Hua Chen, Ming-Chiang Lee, Tsung-Hsun Lee, Chen-Chuan Fan
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Patent number: 9564393Abstract: A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.Type: GrantFiled: September 18, 2015Date of Patent: February 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Yi Huang, Kuo-Hua Chen, Chi-Tsung Chiu
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Publication number: 20160300782Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.Type: ApplicationFiled: April 13, 2015Publication date: October 13, 2016Inventors: Tang-Yuan CHEN, Chin-Li KAO, Kuo-Hua CHEN, Ming-Hung CHEN, Dao-Long CHEN