Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A liquid crystal display includes a liquid crystal panel, a source driving circuit, a timing controller, and a gate driving circuit. The source driving circuit converts frame data into a plurality of data voltages, and charges/discharges a first data line according to a data voltage of the plurality of data voltages. The gate driving circuit enables a gate line corresponding to the data voltage. The timing controller sequentially enables a plurality of switch enable lines corresponding to the gate line. A plurality of pixel switches are turned on according to the enabled gate line. A data line switch is turned on according to an enabled switch enable line. The data voltage charges/discharges a corresponding pixel through the turned-on data line switch and one of the turned-on pixel switches.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract: A shift register includes a signal input unit for receiving and providing an input signal, a signal output unit for controlling whether outputting a clock signal according to the input signal provided by the signal input unit, and a plurality of stable modules. Each of the stable modules is electrically coupled to an output terminal of the signal input unit, an output terminal of the signal output unit, and a default potential. Each of the stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, such that both the output terminal of the signal input unit and the output terminal of the signal output unit are electrically coupled to the default potential when the input signal is disabled. Before one of the stable modules is disabled, another of the stable modules has already been enabled.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. The Nth shift register stage of the shift register stages includes an input unit, a pull-up unit and a pull-down unit. The input unit is put in use for outputting an Nth driving control voltage according to an (N?1)th gate signal and an (N?2)th driving control voltage which are generated respectively by the (N?1) th shift register stage and the (N?2) th shift register stage of the shift register stages. The pull-up unit pulls up an Nth gate signal according to the Nth driving control voltage and a system clock. The pull-down unit pulls down the Nth gate signal and the Nth driving control voltage according to an (N+2)th gate signal generated by the (N+2)th shift register stage of the shift register stages.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal.

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

Abstract: A display device having bi-directional shift registers is disclosed. The display device includes a display panel which has N gate lines, a first set of dummy registers, a second set of dummy registers, a plurality of valid shift registers coupled between the two sets of dummy registers, and a first start pulse signal generator coupled to the first valid register for generating the first start pulse signal to the first valid register to enable the first gate line. The first valid register is coupled to the first set of dummy registers. The Nth valid register is coupled to the second set of dummy registers.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract: An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, and pixels. The first and the second scan lines are alternately arranged along a first direction. The data lines are arranged in parallel along a second direction. The pixels are arranged to form first pixel rows and second pixel rows alternately arranged in the first direction. The first pixel row includes first and second pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The second pixel row includes third and fourth pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The pixels between two adjacent data lines are arranged in two columns. Among the pixels in the same column, the pixels in odd rows and in even rows are electrically connected to different data lines, respectively.

Abstract: A shift register comprises a plurality of stages. In one embodiment, each stage includes a first output, a second output, a pull-up circuit electrically coupled between a node and the second output, a pull-up control circuit electrically coupled to the node, a pull-down control circuit electrically coupled between the node and the first output, and a control circuit electrically coupled to the node and the first output.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.