Patents by Inventor Kuo-Hua Pan

Kuo-Hua Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254623
    Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20220246590
    Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Chen-Hua Yu, Kuo-Lung Pan, Ting-Hao Kuo, Hao-Yi Tsai, Hsiu-Jen Lin, Hao-Jan Pei, Ching-Hua Hsieh
  • Publication number: 20220246613
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Publication number: 20220238519
    Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Publication number: 20220216329
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11374006
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-San Chien, Chun-Sheng Liang, Jhon-Jhy Liaw, Kuo-Hua Pan, Hsin-Che Chiang
  • Patent number: 11362096
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device includes a first fin structure. The semiconductor device structure also includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan
  • Patent number: 11349002
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20220157938
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20220149039
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Patent number: 11315785
    Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11315924
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Patent number: 11302692
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Publication number: 20220102509
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Patent number: 11282705
    Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11282942
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11251069
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 11251181
    Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11245005
    Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 11245034
    Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Ming Chang, Ta-Chun Lin, Rei-Jay Hsieh, Yung-Chih Wang, Wen-Huei Guo, Kuo-Hua Pan, Buo-Chin Hsu