Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.

Abstract: A semiconductor structure includes a first well doped with a first dopant and a second well doped with a second dopant different from the first dopant. From a top view, the first well includes a first base extending lengthwise along a direction, and a first letter-shaped portion and a second letter-shaped portion connected to the first base. From the top view, the second well includes a second base extending lengthwise along the direction and a third letter-shaped portion connected to the second base. The third letter-shaped portion extends into the first well and is keyed to the first letter-shaped portion and the second letter-shaped portion.

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a fin-shape base protruding from the semiconductor substrate and extending lengthwise in a first direction, nanostructures suspended above the fin-shape base, a metal gate structure wrapping around each of the nanostructures, an epitaxial feature abutting the nanostructures, and inner spacers interposing the epitaxial feature and the metal gate structure. In a cross section perpendicular to the first direction the fin-shape base includes a first layer and a second layer over the first layer. The first layer has a second lattice constant different from the first lattice constant, and the second layer has a third lattice constant different from the second lattice constant. A portion of the metal gate structure is sandwiched between the second layer and a bottommost one of the nanostructures.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate electrode layer formed over a substrate and a gate spacer structure formed over a sidewall of the gate electrode layer. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate spacer structure and separated from the gate electrode layer by the gate spacer structure. The source/drain contact structure includes a conductive base portion formed over a source/drain region in the substrate and a conductive capping portion with an arched top surface formed over the conductive base portion. The top surface of the conductive base portion is lower than the top surface of the gate electrode layer. The semiconductor device structure further includes a first dielectric capping layer formed over the source/drain contact structure.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.