METHODS OF FORMING GATE-ALL-AROUND (GAA) DEVICES
A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.
This application is a continuation of U.S. patent application Ser. No. 17/409,086, filed on Aug. 23, 2021, entitled “GATE-ALL-AROUND (GAA) METHOD AND DEVICES” which is a divisional of U.S. patent application Ser. No. 16/409,386, filed on May 10, 2019, and entitled “GATE-ALL-AROUND (GAA) METHOD AND DEVICES”, now U.S. Pat. No. 11,101,359 issued on Aug. 24, 2021, which claims priority to U.S. Provisional Patent Application No. 62/772,387, filed on Nov. 28, 2018, which application is hereby incorporated herein by reference.
BACKGROUNDSemiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors.
One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. To achieve these goals, fin FETs (finFETs), multiple gate transistors, and gate all-around (GAA) transistors are being researched and implemented. However, with continuous shrinking dimensions, even this new device structure faces new challenges.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
With reference now to
A first implantation 103 (represented in
Stacks of alternating layers 203a can include any number of the first semiconductor layers 205a (e.g., SiGe layers) and any number of the second semiconductor layers 207a (e.g., Si layers). As illustrated, for example, stack of alternating layers 203a has five first semiconductor layers 205a (e.g., SiGe layers) and four second semiconductor layers 207a (e.g., Si layers. The numbers of first semiconductor layers 205 (e.g., SiGe layers) and second semiconductor layers 207 (e.g., Si layers) may be modulated by the number of cycles of epitaxial growth used to form the first stack of alternating layers, respectively.
After the patterning, the trench 305 is etched as illustrated in
The average thicknesses of first semiconductor layers 205a may be different from the average thicknesses of first semiconductor layers 205b and the average thicknesses of second semiconductor layers 207a may be different from the average thicknesses of second semiconductor layers 207b. The relative average thicknesses of the layers will determine the sheet spacing between nanosheets of the device. Larger sheet spacing can enable thicker input-output (IO) gate oxide on the nanosheets, which is useful for, e.g., IO devices. In an embodiment, the relative average thicknesses of the first semiconductor layers 205 and the second semiconductor layers 207 are determined by controlling the epitaxial growth of the layers through modulating the reactant gas flow rate, the growth temperature, or the time length of the periods of epitaxial growth of each layer. The first semiconductor layers 205b of the second stack of alternating layers 203b may have a thickness greater than the first semiconductor layers 205a of the first stack of alternating layers 203a. The second semiconductor layers 207b of the second stack of alternating layers 203b may have a thickness greater than the second semiconductor layers 207a of the first stack of alternating layers 203a. The average thicknesses of first semiconductor layers 205a may be between about 5 nm to about 30 nm, the average thicknesses of second semiconductor layers 207a may be between about 3 nm to about 30 nm, the average thicknesses of first semiconductor layers 205b may be between about 8 nm to about 40 nm, and the average thicknesses of second semiconductor layers 207b may be between about 3 nm to about 40 nm. The ratio of the average thicknesses of first semiconductor layers 205a to the average thicknesses of second semiconductor layers 207a may be between about 10:1 to about 1:6. The ratio of the average thicknesses of first semiconductor layers 205b to the average thicknesses of second semiconductor layers 207b may be between about 10:1 to about 1:5.
In some embodiments, the material of the first semiconductor layers 205a and 205b is different from the material of the second semiconductor layers 207a and 207b. For example, the first semiconductor layers 205a and 205b may be SiGe layers and the second semiconductor layers 207a and 207b may be Si layers or SiC layers. In another embodiment, for example, the first semiconductor layers 205a and 205b may be Si layers or SiC layers and the second semiconductor layers 207a and 207b may be SiGe layers. The difference in materials may allow for different strains and/or may allow for an etch selectivity between the first semiconductor layers, 205a and 205b, and the second semiconductor layers, 207a and 207b, as will be apparent below.
In
Fins 303a and 303b may be patterned to have different widths varied from 4 to 100 nm. For example, in an embodiment, the width of fin 303a may be between about 4 nm to about 100 nm, and the width of fin 303b may be between about 4 nm to about 100 nm. The ratio of the width of fin 303a to the width of fin 303b may be between about 25:1 to about 1:25. The patterning of the fins 303 will determine the widths of the nanosheets (sheet width) produced from the fins in following steps. Larger sheet width (or Weff, the NS effective width), can enable higher speed performance. Smaller Weff can enable lower power applications.
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A first hardmask layer 413 is deposited over the dummy metal layer 411 through a process such as CVD, or a spin-on-glass process, although any acceptable process may be utilized. In an embodiment, the first hardmask layer 413 may be an oxide layer (e.g., silicon oxide). A second hardmask layer 415 is then deposited on the first hardmask layer 413 through a process such as CVD, or a spin-on-glass process, although any acceptable process may be utilized. The first hardmask layer 413 and the second hardmask layer 415 are patterned to form a dummy gate hardmask layer stack 417 over the dummy metal layer 411. In an embodiment, a polysilicon etch and a dummy oxide removal process are performed using the dummy gate hardmask layer stack 417 to pattern the dummy metal layer 411 and the dummy gate oxide layer 401. During patterning, portions of the dummy metal layer 411 and portions of the dummy gate oxide layer 401 are removed from source/drain areas of fins 303 and portions of the dummy metal layer 411 and portions of the dummy gate oxide layer 401 remain over a channel region of fins 303 to form a dummy metal gate electrode 412. The dummy metal gate electrode 412 includes the patterned dummy metal layer 411 and the patterned dummy gate oxide layer 401 disposed below the patterned dummy metal layer 411. The dummy metal gate electrode 412 and the dummy gate hardmask layer stack 417 collectively form the dummy metal gate stack 419.
The dummy metal gate stack 419 will be used to define and form source/drain regions from the exposed portions of fins 303. The dummy metal gate stack 419 will then be removed to allow processing to be performed to define and form channel regions from the exposed portions of fins 303, center portions of fins 303, as follows.
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The epitaxial source/drain regions 503 may be implanted with dopants followed by an anneal process. The implanting process may include forming and patterning masks such as a photoresist to cover the regions of the GAA FET device that are to be protected from the implanting process. The source/drain regions 503 may have an impurity (e.g., dopant) concentration in a range from about 1E19 cm−3 to about 1E21 cm−3. P-type impurities, such as boron or indium, may be implanted in the source/drain region 503 of a P-type transistor. N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain regions 503 of an N-type transistor. In some embodiments, the epitaxial source/drain regions may be in situ doped during growth.
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Furthermore, while not specifically illustrated, it is to be understood that an NFET device may be formed in the channel region from any one of the fins 303 or a PFET device may be formed in the channel region from any one of the fins 303. While not specifically illustrated, it is also to be understood that an NFET device may be formed in a channel region from one of the fins 303 and a PFET device may be formed in a channel region from the other one of the fins 303. For example, in an embodiment in which two NFET devices are formed, the selectively removed first semiconductor layers 205a and 205b may comprise SiGe, the remaining second semiconductor layers 207a and 207b may comprise Si, and source/drain regions 503 may comprise silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like. In another embodiment in which two PFET devices are formed, the selectively removed first semiconductor layers 205a and 205b may comprise Si, the remaining second semiconductor layers 207a and 207b may comprise SiGe, and source/drain regions 503 comprise SiGe and a p-type impurity such as boron or indium. In other embodiments in which two PFETs may be formed, the selectively removed first semiconductor layers 205a and 205b may comprise SiGe, the remaining second semiconductor layers 207a and 207b may comprise Si, and source/drain regions 503 comprise SiGe and a p-type impurity such as boron or indium.
After the selective removal of the first semiconductor layers 205a and 205b, the second semiconductor layers 207a and 207b remain in fins 303 and are referred to herein as a first stack of nanosheets 407a and a second stack of nanosheets 407b, respectively. GAA transistor devices using the nanosheet structures can be logic devices, static random access memory (SRAM) devices, IO devices, electro-static discharge (ESD) devices, or passive devices. In another embodiment, after etching, bottom-most first semiconductor layers 205a and 205b (e.g., SiGe layers) may remain below the upper surface of the STIs 313 as a stress layer within the fins 303a and 303b to provide certain strains or relaxations of the fin materials.
In an embodiment in which the first semiconductor layers 205a and 205b (e.g., SiGe layers) are formed of silicon germanium (SiGe) and the second semiconductor layers 207a and 207b (e.g., Si layers) are formed of silicon (Si), the second semiconductor layers 207a and 207b (e.g., Si layers) may be removed, for example, by a Si removal process. In some embodiments, the removal process may use a wet etch using a tetramethylammonium hydroxide (TMAH) solution, or the like. Other processes and materials may be used. This etching process removes the second semiconductor layers 207a and 207b. Thus, second nanosheets 405a and 405b (not specifically shown) are formed from fins 303.
In
First and second gate dielectrics 521a and 521b may be formed to have different respective thicknesses, as illustrated in
First and second gate dielectrics 521a and 521b may also be formed to have different compositions. For example, the first gate dielectric 521a may comprise SiO2, SiON, Si3N4, HfOx, LaOx, and/or AlOx and the second gate dielectric 521b may comprise a varied ratio of SiO2, SiON, Si3N4, HfOx, LaOx, and/or AlOx from the first gate dielectric 521a.
In
In
First, second, and third gate dielectrics 521a, 521b, and 521c may be formed to have different respective thicknesses. Thicker gate dielectrics are useful for IO devices and thinner gate dielectrics are useful for core devices. The relative average thicknesses of the first, second, and third gate dielectrics 521a, 521b, and 521c may be determined by modulating the time length of the periods of deposition for the gate dielectrics. In an embodiment, an average thickness of the first gate dielectric 521a may be between about 1 nm to about 5 nm, an average thickness of the second gate dielectric 521b may be between about 2.5 nm to about 7 nm, and an average thickness of the third gate dielectric 521c may be between about 1 nm to about 7 nm. In an embodiment, the average thickness of the third gate dielectric 521c is substantially greater than the average thickness of the first gate dielectric 521a and substantially smaller than the average thickness of the second gate dielectric 521b in order to use the third gate dielectric 521c as part of a device with enhanced reliability using lower power.
First, second, and third gate dielectrics 521a, 521b, and 521c may also be formed to have different compositions. For example, the first gate dielectric 521a may comprise SiO2, SiON, Si3N4, HfOx, LaOx, and/or AlOx, and the second gate dielectric 521b and the third gate dielectric 521c may comprise varied ratios of SiO2, SiON, Si3N4, HfOx, LaOx, and/or AlOx from the first gate dielectric 521a.
In
The embodiments disclosed above include methods for fabrication of GAA transistors that allow for the modulation of nanosheet (NS) width, NS thickness, NS space, and stack number. This modulation of NS structures can be employed on single wafers. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage. Larger NS width can enable higher speed performance and smaller NS width and/or stack number reduction can enable lower power applications. Increasing sheet space, the distance between adjacent nanosheets in a stack, enables the use of thicker IO gate oxide which can be used for fulfilling NS structure input-output (IO) devices. GAA transistor devices using the NS structures can be fabricated nearby each other or far away from each other, and can be used for logic devices, static random access memory (SRAM) devices, IO devices, electro-static discharge (ESD) devices, or passive devices.
In accordance with an embodiment, a method of manufacturing a device includes: forming a first stack of alternating layers on a substrate, wherein forming the first stack of alternating layers includes depositing alternating first layers of a first semiconductor material and second layers of a second semiconductor material different from the first semiconductor material on the substrate; forming a second stack of alternating layers on the substrate at a first distance from the first stack of alternating layers, wherein forming the second stack of alternating layers includes depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material on the substrate, wherein the first layers of the second stack of alternating layers have a thickness greater than the first layers of the first stack of alternating layers; constructing a first stack of nanosheets from the first stack of alternating layers and a second stack of nanosheets from the second stack of alternating layers, wherein the constructing the first and second stack of nanosheets includes: patterning a first fin from the first stack of alternating layers and a second fin from the second stack of alternating layers; and removing the first layers from the first stack of alternating layers and removing the first layers from the second stack of alternating layers, such that the distances between adjacent remaining layers of the second stack of alternating layers are greater than the distances between adjacent remaining layers of the first stack of alternating layers; and forming a first gate dielectric over the first stack of nanosheets and a second gate dielectric over the second stack of nanosheets. In an embodiment, the first gate dielectric is formed to include a first gate dielectric thickness and the second gate dielectric is formed to include a second gate dielectric thickness greater than the first gate dielectric thickness. In an embodiment, the first and second gate dielectrics are formed to include different materials. In an embodiment, the first stack of alternating layers is formed to include a first number of alternating layers by controlling the number of cycles of epitaxial growth used to form the first stack of alternating layers, wherein the second stack of alternating layers is formed to include a second number of alternating layers by controlling the number of cycles of epitaxial growth used to form the second stack of alternating layers, and wherein the first number is different from the second number. In an embodiment, the second layers of the second stack of alternating layers are formed to have a thickness greater than the second layers of the first stack of alternating layers.
In accordance with another embodiment, a method of manufacturing a device includes: etching a recess in a first stack of alternating layers, wherein the first stack of alternating layers includes alternating first layers including a first semiconductor material and second layers including a second semiconductor material different from the first semiconductor material on a substrate, wherein the first layers of the first stack of alternating layers have a first average thickness and the second layers of the first stack of alternating layers have a second average thickness, wherein the first average thickness and the second average thickness are determined by controlling epitaxial growth of the first and second layers of the first stack of alternating layers; forming a second stack of alternating layers within the first stack of alternating layers, wherein the forming the second stack of alternating layers includes depositing alternating first layers including the first semiconductor material and second layers including the second semiconductor material in the recess, wherein the first layers of the second stack of alternating layers have a third average thickness and the second layers of the second stack of alternating layers have a fourth average thickness, wherein the third average thickness is different from the first average thickness and wherein the fourth average thickness is different from the second average thickness, wherein the third average thickness and the fourth average thickness are determined by controlling epitaxial growth of the first and second layers of the second stack of alternating layers; constructing a first stack of nanosheets from the first stack of alternating layers and a second stack of nanosheets from the second stack of alternating layers, wherein constructing the first and second stack of nanosheets includes: patterning a first fin from the first stack of alternating layers and a second fin from the second stack of alternating layers; removing one out of the first layers and the second layers from the first stack of alternating layers and the second stack of alternating layers; and forming a first gate dielectric over the first stack of nanosheets and a second gate dielectric over the second stack of nanosheets. In an embodiment, the first stack of nanosheets is formed to have a first width, the second stack of nanosheets is formed to have a second width, and the first width is different from the second width. In an embodiment, the first and second stacks of nanosheets are formed to include different numbers of nanosheets. In an embodiment, forming the second stack of alternating layers further includes: forming a spacer on sidewalls of the recess; and depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material in the recess between sidewalls of the spacer. In an embodiment, patterning the second fin includes etching away the spacer. In an embodiment, forming a second stack of alternating layers further includes depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material conformally on a bottom and sidewalls of the recess. In an embodiment, patterning the second fin includes etching away an outer portion of the second stack of alternating layers such that the remaining portion includes only alternating horizontal first layers of the first semiconductor material and horizontal second layers of the second semiconductor material.
In accordance with yet another embodiment, a device includes: a first stack of nanosheets, wherein each nanosheet of the first stack of nanosheets is surrounded by a first gate dielectric, wherein adjacent nanosheets of the first stack of nanosheets are separated by a first average spacing; and a second stack of nanosheets located at a first distance from the first stack of nanosheets, wherein each nanosheet of the second stack of nanosheets is surrounded by a second gate dielectric, wherein adjacent nanosheets of the second stack of nanosheets are separated by a second average spacing, wherein the second average spacing is greater than the first average spacing. In an embodiment, the first gate dielectric has a first average thickness, the second gate dielectric has a second average thickness, and the second average thickness is greater than the first average thickness. In an embodiment, the first and second stacks of nanosheets include different numbers of nanosheets. In an embodiment, the nanosheets of the first stack of nanosheets have a first average thickness, the nanosheets of the second stack of nanosheets have a second average thickness, and the second average thickness is greater than the first average thickness. In an embodiment, the first stack of nanosheets includes part of a logic device and wherein the second stack of nanosheets includes part of an IO device. In an embodiment, a third stack of nanosheets is located at a second distance from the first stack of nanosheets such that the second distance is less than the first distance, and wherein the first stack of nanosheets has a first width and wherein the third stack of nanosheets has a second width, such that the first width is greater than the second width. In an embodiment, a third stack of nanosheets is located at a second distance from the first stack of nanosheets such that the second distance is less than the first distance, wherein each nanosheet of the third stack of nanosheets is surrounded by a third gate dielectric, wherein the first gate dielectric has a first average thickness, wherein the second gate dielectric has a second average thickness, and wherein the third gate dielectric has a third average thickness, such that the third average thickness is greater than the first average thickness and such that the third average thickness is less than the second average thickness. In an embodiment, a third stack of nanosheets is located at a second distance from the first stack of nanosheets such that the second distance is less than the first distance, and wherein the first and third stacks of nanosheets include different numbers of nanosheets.
Advantageous features of some embodiments disclosed herein include a method of manufacturing a device, the method including epitaxially growing alternating layers of channel material and sacrificial material on a substrate, etching a recess into the alternating layers of channel material and sacrificial material, lining sidewalls of the recess with a liner material, epitaxially growing alternating layers of second channel material and second sacrificial material in the recess, etching the alternating layers of channel material and sacrificial material to form a first transistor structure and etching the alternating layers of second channel material and second sacrificial material to form a second transistor fin structure laterally displaced from the first transistor structure. The method further includes forming a dummy gate over the first transistor structure and the second transistor fin structure, forming source/drain features adjacent respective sides of the dummy gate, removing the sacrificial material and the second sacrificial material to form first gaps between respective layers of channel material in the first transistor structure and second gaps between respective layers of second channel material, the second gaps being greater in thickness than the first gaps, depositing a gate dielectric material to a first thickness surrounding respective layers of channel material in the first gaps to form lined first gaps, and depositing the gate dielectric material to a second thickness, greater than the first thickness, surrounding respective layers of second channel material in the second gaps to form lined second gaps, and depositing gate electrodes filling the lined first gaps and the lined second gaps.
Advantageous features of other embodiments disclosed herein include a method of manufacturing a device by depositing a first stack of alternating layers of channel material and sacrificial material onto a substrate, etching a recess into the first stack of alternating layers of channel material and sacrificial material, the recess exposing a portion of the substrate, and conformally depositing a liner material on sidewalls and a bottom surface of the recess to form a lined recess. The method further includes depositing a second stack of alternating layers of second channel material and second sacrificial material to fill the lined recess, patterning the first stack of alternating layers and the underlying substrate to form a first fin structure, the first fin structure including a stack of first channel regions separated by first sacrificial material regions, patterning the second stack of alternating layers and the underlying substrate to form a second fin structure, the second fin structure comprising a second stack of second channel regions separated by second sacrificial material regions, and forming an isolation structure between the first fin structure and the second fin structure. The method also includes forming a first dummy gate structure over the first fin structure and a second dummy gate structure over the second fin structure, forming first source/drain regions in the first fin structure and second source/drain regions in the second fin structure, removing the first sacrificial material regions and removing the second sacrificial material regions; and forming a gate structure surrounding individual first channel regions and a gate structure surrounding individual second channel regions.
Still other embodiments disclosed herein provide advantageous features such as a method of manufacturing a device, including depositing alternating first layers of first semiconductor material and second layers of second semiconductor material different from the first semiconductor material on a substrate, patterning the alternating first layers of first semiconductor material and second layers of second semiconductor material to form a recess therein, while leaving a remaining portion of the first layers of first semiconductor material and second layers of second semiconductor material un-patterned; lining the recess to form a lined recess, and filling the lined recess by depositing alternating third layers of first semiconductor material and fourth layers of second semiconductor material within the lined recess, wherein respective third layers of first semiconductor material have a different average thickness than do respective first layers of first semiconductor material, and further wherein respective fourth layers of second semiconductor material have a different average thickness than do respective second layers of second semiconductor material. The method also includes patterning a remaining portion of the alternating first layers of first semiconductor material and second layers of second semiconductor material to form therefrom a first stack of nanosheets, and patterning the alternating third layers of first semiconductor material and fourth layers of second semiconductor material to form therefrom a second stack of nanosheets horizontally spaced apart from the first stack of nanosheets, removing the first layers of first semiconductor material from the first stack of nanosheets to form a first stack of channel regions, comprised of the second layers of second semiconductor material, and vertically separated from one another by a first spacing, removing the third layers of first semiconductor material from the second stack of nanosheets to form a second stack of channel regions, comprised of the fourth layers of second semiconductor material, and vertically separated from one another by a second spacing, the second spacing being different than the first spacing, forming a first gate structure surrounding individual channel regions of the first stack of channel regions, and forming a second gate structure surrounding individual channel regions of the second stack of channel regions.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method of manufacturing a device, comprising:
- depositing alternating first layers of first semiconductor material and second layers of second semiconductor material different from the first semiconductor material on a substrate;
- patterning the alternating first layers of first semiconductor material and second layers of second semiconductor material to form a recess therein, while leaving a remaining portion of the first layers of first semiconductor material and second layers of second semiconductor material un-patterned;
- lining the recess to form a lined recess;
- filling the lined recess by depositing alternating third layers of first semiconductor material and fourth layers of second semiconductor material within the lined recess, wherein respective third layers of first semiconductor material have a different average thickness than do respective first layers of first semiconductor material, and further wherein respective fourth layers of second semiconductor material have a different average thickness than do respective second layers of second semiconductor material;
- patterning a remaining portion of the alternating first layers of first semiconductor material and second layers of second semiconductor material to form therefrom a first stack of nanosheets, and patterning the alternating third layers of first semiconductor material and fourth layers of second semiconductor material to form therefrom a second stack of nanosheets horizontally spaced apart from the first stack of nanosheets;
- removing the first layers of first semiconductor material from the first stack of nanosheets to form a first stack of channel regions, comprised of the second layers of second semiconductor material, and vertically separated from one another by a first spacing;
- removing the third layers of first semiconductor material from the second stack of nanosheets to form a second stack of channel regions, comprised of the fourth layers of second semiconductor material, and vertically separated from one another by a second spacing, the second spacing being different than the first spacing;
- forming a first gate structure surrounding individual channel regions of the first stack of channel regions; and
- forming a second gate structure surrounding individual channel regions of the second stack of channel regions.
2. The method of claim 1, wherein the step of lining the recess to form the lined recess comprises conformally growing a layer of the first semiconductor material in the recess.
3. The method of claim 2, wherein the layer of the first semiconductor material in the recess is epitaxially grown from the substrate and from sidewalls of the alternating first layers of first semiconductor material and second layers of second semiconductor material that define sidewalls of the recess.
4. The method of claim 1, wherein the step of lining the recess to form the lined recess comprises conformally depositing a liner material within the recess.
5. The method of claim 4, further comprising removing the liner material from a bottom of the recess while leaving the liner material along sidewalls of the recess.
6. The method of claim 4, wherein the step of and patterning the alternating third layers of first semiconductor material and fourth layers of second semiconductor material to form therefrom a second stack of nanosheets removes the liner material.
7. The method of claim 1, wherein step of forming a first gate structure includes forming a first gate dielectric material on individual channel regions of the first stack of channel regions and forming a first gate electrode on the first gate dielectric material, and further wherein the step of forming a second gate structure includes forming a second gate dielectric material, different from the first gate dielectric material on individual channel regions of the second stack of channel regions and forming the first gate electrode on the second gate dielectric material.
8. The method of claim 1, wherein the first stack of channel regions has a first width when viewed in a first direction and the second stack of channel regions has a second width when viewed in the first direction, the first width being greater than the second width.
9. The method of claim 1, wherein the step of patterning the remaining portion of the alternating first layers of first semiconductor material and second layers of second semiconductor material to form therefrom the first stack of nanosheets includes patterning a portion of the substrate underlying the first stack of nanosheets to form a fin structure.
10. A method of manufacturing a device, comprising:
- depositing a first stack of alternating layers of channel material and sacrificial material onto a substrate;
- etching a recess into the first stack of alternating layers of channel material and sacrificial material, the recess exposing a portion of the substrate;
- conformally depositing a liner material on sidewalls and a bottom surface of the recess to form a lined recess;
- depositing a second stack of alternating layers of second channel material and second sacrificial material to fill the lined recess;
- patterning the first stack of alternating layers and the underlying substrate to form a first fin structure, the first fin structure including a stack of first channel regions separated by first sacrificial material regions;
- patterning the second stack of alternating layers and the underlying substrate to form a second fin structure, the second fin structure comprising a second stack of second channel regions separated by second sacrificial material regions;
- forming an isolation structure between the first fin structure and the second fin structure;
- forming a first dummy gate structure over the first fin structure and a second dummy gate structure over the second fin structure;
- forming first source/drain regions in the first fin structure and second source/drain regions in the second fin structure;
- removing the first sacrificial material regions and removing the second sacrificial material regions; and
- forming a gate structure surrounding individual first channel regions and a gate structure surrounding individual second channel regions.
11. The method of claim 10, wherein the step of conformally depositing a liner material on sidewalls and a bottom surface of the recess to form a lined recess comprises conformally growing a layer of second channel material in the recess.
12. The method of claim 11, wherein the layer of second channel material is epitaxially grown from the substrate and from sidewalls of the recess.
13. The method of claim 10, wherein the step of lining the recess to form the lined recess comprises conformally depositing a liner material within the recess.
14. The method of claim 10, further comprising removing the liner material from a bottom of the recess while leaving the liner material along sidewalls of the recess.
15. The method of claim 10, wherein the first fin structure has a first number of layers of channel region material and the second fin structure has a second number of layers of second channel region material, the second number being lesser than the first number.
16. The method of claim 10, wherein the channel material and the second channel material comprise the same semiconductor material.
17. The method of claim 10, wherein the sacrificial material and the second sacrificial material comprises the same semiconductor material.
18. A method of manufacturing a device, comprising:
- epitaxially growing alternating layers of channel material and sacrificial material on a substrate;
- etching a recess into the alternating layers of channel material and sacrificial material;
- lining sidewalls of the recess with a liner material;
- epitaxially growing alternating layers of second channel material and second sacrificial material in the recess;
- etching the alternating layers of channel material and sacrificial material to form a first transistor structure and etching the alternating layers of second channel material and second sacrificial material to form a second transistor fin structure laterally displaced from the first transistor structure;
- forming a dummy gate over the first transistor structure and the second transistor fin structure;
- forming source/drain features adjacent respective sides of the dummy gate;
- removing the sacrificial material and the second sacrificial material to form first gaps between respective layers of channel material in the first transistor structure and second gaps between respective layers of second channel material, the second gaps being greater in thickness than the first gaps;
- depositing a gate dielectric material to a first thickness surrounding respective layers of channel material in the first gaps to form lined first gaps, and depositing the gate dielectric material to a second thickness, greater than the first thickness, surrounding respective layers of second channel material in the second gaps to form lined second gaps; and
- depositing gate electrodes filling the lined first gaps and the lined second gaps.
19. The method of claim 18, wherein the method further comprises epitaxially growing a first number of layers of channel material and epitaxially growing a second number of layers of second channel material, different than the first number.
20. The method of claim 18, wherein the step of lining sidewalls of the recess with a liner material includes a process selected from the group consisting of:
- conformally depositing a spacer liner on sidewalls and the bottom of the recess and removing the spacer line from the bottom of the recess; and
- epitaxially growing a first layer of second channel material on sidewalls and the bottom of the recess.
Type: Application
Filed: Jul 1, 2024
Publication Date: Oct 24, 2024
Inventors: Shien-Yang Wu (Jhudong Town), Ta-Chun Lin (Hsinchu), Kuo-Hua Pan (Hsinchu)
Application Number: 18/760,602