Patents by Inventor Kuo-Hung Lo
Kuo-Hung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11864368Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.Type: GrantFiled: June 2, 2022Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jordan Hsu, Yu-Kuan Lin, Shau-Wei Lu, Chang-Ta Yang, Ping-Wei Wang, Kuo-Hung Lo
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Publication number: 20230413503Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.Type: ApplicationFiled: August 7, 2023Publication date: December 21, 2023Inventors: Shau-Wei LU, Hao Chang, Kun-Hsi Li, Kuo-Hung Lo, Kang-Yu Hsu, Yao-Chung Hu
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Patent number: 11832429Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.Type: GrantFiled: December 21, 2020Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shau-Wei Lu, Hao Chang, Kun-Hsi Li, Kuo-Hung Lo, Kang-Yu Hsu, Yao-Chung Hu
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Publication number: 20230276608Abstract: A static random access memory device is provided and includes a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate and a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of a substrate. A boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO
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Patent number: 11683924Abstract: A static random access memory device includes a first gate of a write port circuit disposed in a standard threshold voltage region of a substrate and a second gate of a read port circuit disposed in a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. A distance between a first edge, corresponding to an edge of the first gate, and a boundary, between the standard threshold voltage region and the low threshold voltage region, is different from a distance between the boundary and a second edge, corresponding to an edge of the second gate.Type: GrantFiled: March 18, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
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Patent number: 11641729Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.Type: GrantFiled: December 19, 2019Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jordan Hsu, Yu-Kuan Lin, Shau-Wei Lu, Chang-Ta Yang, Ping-Wei Wang, Kuo-Hung Lo
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Publication number: 20220384455Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO
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Patent number: 11462550Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.Type: GrantFiled: August 17, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
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Publication number: 20220302130Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jordan HSU, Yu-Kuan LIN, Shau-Wei LU, Chang-Ta YANG, Ping-Wei WANG, Kuo-Hung LO
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Publication number: 20220208774Abstract: A static random access memory device includes a first gate of a write port circuit disposed in a standard threshold voltage region of a substrate and a second gate of a read port circuit disposed in a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. A distance between a first edge, corresponding to an edge of the first gate, and a boundary, between the standard threshold voltage region and the low threshold voltage region, is different from a distance between the boundary and a second edge, corresponding to an edge of the second gate.Type: ApplicationFiled: March 18, 2022Publication date: June 30, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO
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Patent number: 11355499Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.Type: GrantFiled: December 19, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jordan Hsu, Yu-Kuan Lin, Shau-Wei Lu, Chang-Ta Yang, Ping-Wei Wang, Kuo-Hung Lo
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Patent number: 11282842Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.Type: GrantFiled: November 13, 2020Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
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Publication number: 20210183870Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.Type: ApplicationFiled: December 21, 2020Publication date: June 17, 2021Inventors: Shau-Wei LU, Hao CHANG, Kun-Hsi LI, Kuo-Hung LO, Kang-Yu HSU, Yao-Chung HU
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Publication number: 20210066312Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO
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Patent number: 10872896Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.Type: GrantFiled: September 30, 2019Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shau-Wei Lu, Hao Chang, Kun-Hsi Li, Kuo-Hung Lo, Kang-Yu Hsu, Yao-Chung Hu
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Patent number: 10868019Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.Type: GrantFiled: May 5, 2020Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo, Ping-Wei Wang
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Publication number: 20200381441Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO
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Patent number: 10840251Abstract: A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor.Type: GrantFiled: May 20, 2019Date of Patent: November 17, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
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Publication number: 20200266200Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO, Ping-Wei WANG
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Patent number: 10748911Abstract: An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.Type: GrantFiled: June 27, 2018Date of Patent: August 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo