Patents by Inventor Kuo-Hung Wang
Kuo-Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Patent number: 11967594Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240128178Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.Type: ApplicationFiled: February 8, 2023Publication date: April 18, 2024Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
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Publication number: 20240105644Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.Type: ApplicationFiled: January 6, 2023Publication date: March 28, 2024Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20240096895Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240088026Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.Type: ApplicationFiled: January 17, 2023Publication date: March 14, 2024Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
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Patent number: 11515185Abstract: In an embodiment, a system includes: a chuck; multiple groove conduits arranged around a circumference of a wafer position on the chuck; a gas source in fluid communication with the multiple groove conduits; and a flow monitor configured to determine an amount of gas flow from the gas source to an individual one of the multiple groove conduits.Type: GrantFiled: May 5, 2021Date of Patent: November 29, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Kuo-Hung Wang
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Publication number: 20210257237Abstract: In an embodiment, a system includes: a chuck; multiple groove conduits arranged around a circumference of a wafer position on the chuck; a gas source in fluid communication with the multiple groove conduits; and a flow monitor configured to determine an amount of gas flow from the gas source to an individual one of the multiple groove conduits.Type: ApplicationFiled: May 5, 2021Publication date: August 19, 2021Inventor: Kuo-Hung WANG
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Patent number: 11010094Abstract: A task management method is disclosed. The method includes sending a query command by a host to an electronic storage device at a variable interval to determine a status of a task queue of the electronic storage device; obtaining a response information. The response information includes a status of the task queue, and the status of the task queue includes an information about whether a task preparation in the task queue is to be completed.Type: GrantFiled: February 11, 2019Date of Patent: May 18, 2021Assignee: MediaTek Singapore Pte. Ltd.Inventors: Jiajie Hao, Kuo-Hung Wang, Liang Li
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Patent number: 11004711Abstract: In an embodiment, a system includes: a chuck; multiple groove conduits arranged around a circumference of a wafer position on the chuck; a gas source in fluid communication with the multiple groove conduits; and a flow monitor configured to determine an amount of gas flow from the gas source to an individual one of the multiple groove conduits.Type: GrantFiled: August 13, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Kuo-Hung Wang
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Publication number: 20190369919Abstract: A task management method is disclosed. The method includes sending a query command by a host to an electronic storage device at a variable interval to determine a status of a task queue of the electronic storage device; obtaining a response information. The response information includes a status of the task queue, and the status of the task queue includes an information about whether a task preparation in the task queue is to be completed.Type: ApplicationFiled: February 11, 2019Publication date: December 5, 2019Inventors: Jiajie Hao, Kuo-Hung Wang, Liang Li
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Publication number: 20100332922Abstract: A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.Type: ApplicationFiled: March 11, 2010Publication date: December 30, 2010Applicant: MEDIATEK INC.Inventors: Po-Wei Chang, Kun-Hung Hsieh, Li-Chun Tu, Ting-Chun Chang, Kuo-Hung Wang
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Publication number: 20100274933Abstract: A solid state disk drive is provided. The solid state disk drive includes a memory device and a controller. The memory device includes memory cells for storing data bits. The controller is coupled to the memory device, accesses the memory device according to a clock signal, estimates a work load of the memory device, and adjusts a frequency of the clock signal in accordance with the estimated work load.Type: ApplicationFiled: November 11, 2009Publication date: October 28, 2010Applicant: MEDIATEK INC.Inventor: Kuo-Hung Wang