METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME
A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.
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This application claims the benefit of U.S. Provisional Application No. 61/221,569 filed Jun. 30, 2009, and entitled “Apparatus and Operation Method of Flash Memory System”. The entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a method for managing a memory device, and more particularly to a method for managing a memory device that extends the operating lifespan of the memory device.
2. Description of the Related Art
Flash memory is widely used in electronic products today, especially for portable applications, as a result of its non-volatility and in system re-programmability. The basic structure of a flash memory cell includes a control gate, a drain diffusion region and a source diffusion region disposed on a substrate to form a transistor with a floating gate under the control gate serving as an electron storage device. The channel region lies under the floating gate with a tunnel oxide insulation layer therebetween. The energy barrier of the tunnel oxide insulation layer can be overcome by applying a sufficiently high electric field thereacross. This allows electrons to pass through the tunnel oxide insulation layer, which is used to change the amount of electrons stored in the floating gate. The amount of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. The Vt of a cell is used to represent the stored data of the cell.
Generally, a flash memory, which can store one bit of data in a cell, is called a Single Level Cell (SLC). Meanwhile, a flash memory, which can store more than one bit of data in a cell, is called a Multiple Level Cell (MLC). Multiple Level Cell (MLC) technology has attracted a lot of attention due to its area efficiency. By storing 2N discrete levels of Vt, the MLC can store N bits of data per cell, thus reducing the equivalent cell size to 1/N. Because of the advantage of multiple bits of data per cell, the MLC has become one of the best candidates for mass storage applications that typically require higher and higher densities.
Although the MLC is more area efficient than the SLC, one drawback of using the MLC is its relatively short operating lifespan. Generally, the maximum amount of erasing of an MLC memory block is about 10K times, versus about 100K times for an SLC memory block. Thus, a method for managing a multiple level cell flash memory device that extends the operating lifespan thereof is highly desired.
BRIEF SUMMARY OF THE INVENTIONSolid state disk drives and methods for managing a memory device are provided. An embodiment of a solid state disk drive comprises a multiple level cell (MLC) memory device and a controller. The MLC memory device comprises a plurality of memory blocks each comprising a plurality of memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.
An embodiment of a method for managing a memory device, comprising a plurality of memory blocks each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, comprises: receiving desired data in accordance with a write operation of the memory device; estimating a failure probability of at least one memory block to be written corresponding to the write operation; and writing the desired data to the memory cells of the memory block in a single level cell (SLC) manner when the estimated failure probability thereof exceeds a predetermined threshold.
Another embodiment of a solid state disk drive comprises a multi-channel multiple level cell (MLC) memory device and a controller. The multi-channel MLC memory device comprises a plurality of memory modules each comprising a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages. Each page is grouped into one of a plurality of page groups in accordance with different page properties. The controller receives at least one program command from a host to write desired data to the multi-channel MLC memory device, allocates a predetermined number of empty pages each belonging to different memory modules in accordance with the program command, and writes the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
Another embodiment of a method for managing a multi-channel memory device comprising a plurality of memory modules each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, comprises: grouping each page into one of a plurality of page groups in accordance with different page properties; receiving at least one program command to write desired data to the multi-channel MLC memory device; allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command; and writing the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The buffer 103 stores data, including the data transferred from the host interface 101 via the controller 102 during a write operation, prior to transferring the data to the memory device 104. Also, during a read operation, the buffer 103 temporarily stores data from the memory device 104 via the controller 102 prior to transferring the data to the host interface 101. According to an embodiment of the invention, the buffer 103 is a random access memory (RAM), such as a dynamic random access memory (DRAM). The memory device 104 may comprise a plurality of memory blocks each with a plurality of memory cells, wherein each memory cell is capable of storing one or more bits. In a preferred embodiment, the memory device may also be configured in an array having a plurality of rows and/or columns of memory modules.
The memory devices 104 and 204 may be multi level cell (MLC) flash memories capable of storing more than a single bit of data per cell. According to an embodiment of the invention, in order to maximize the limited operating lifespan of the MLC memory devices (such as 104 or 204), the memory cells of the MLC memory device may further be transformed into a single level cell (SLC)-like memory cell. As an example, the controller 102 may transform a memory block into an SLC-like memory block when the controller 102 determines that the operating lifespan of the memory block, when being operated in an MLC manner, is about to expire or a failure probability thereof exceeds a predetermined threshold.
According to the embodiment of the invention, when the processor 102 detects that the erase count of the memory block has reached a predetermined erase count threshold THEC or the write operation of the corresponding memory block has failed, the processor 102 may determine that a failure probability of the corresponding memory block is higher than the predetermined threshold. In other words, the memory block may soon become a defective block. The processor 102 next checks whether the corresponding memory block can be transformed into an SLC-like memory block (Step S204). The information may be stored in the header or redundant section of the memory block. If the memory block can be transformed into and/or accessed as an SLC-like memory block, in order to maximize the operating lifespan of the MLC memory block, the memory block is transformed into an SLC-like memory block so as to be accessed in an SLC manner (Step S205). As an example, the memory block may be marked as an SLC-like memory block in the header or redundant section of the memory block as previously described. Meanwhile, if the memory block can not be transformed into an SLC-like memory block (for example, the memory block is already an SLC-like memory block, or is designed not to be transformed into an SLC-like memory block, or others), the processor 102 may mark the memory block as a defective block (Step S206) so that the memory block may not be further programmed or accessed anymore to avoid undesired errors. It should be noted that for clear illustration of the invention concept, only the steps involved by the proposed method are illustrated in
According to the embodiment of the invention, when the processor 102 detects that the read operation of the corresponding memory block has failed or the BER of the memory block has exceeded a predetermined BER threshold THBER, the processor 102 may determine that a failure probability of the corresponding memory block is higher than the predetermined threshold. In other words, the memory block may soon become a defective block. The processor 102 next checks whether the corresponding memory block can be transformed into an SLC-like memory block (Step S304). The information may be, as previously described, stored in the header or redundant section of the memory block. If the memory block can be transformed into and/or accessed as an SLC-like memory block, in order to maximize the operating lifespan of the MLC memory block, the memory block is transformed into an SLC-like memory block so as to be accessed in an SLC manner (Step S305). As an example, the memory block may be marked as an SLC-like memory block in the header or redundant section of the memory block as previously described. Meanwhile, if the memory block can not be transformed into an SLC-like memory block (for example, the memory block is already an SLC-like memory block, or is designed not to be transformed into an SLC-like memory block, or others), the processor 102 may mark the memory block as a defective block (Step S306) so that the memory block may not be further programmed or accessed to avoid undesired errors. It should be noted that for clear illustration of the invention concept, only the steps involved by the proposed method are illustrated in
For an MLC flash memory device, each memory cell may be associated with a plurality of pages. As an example, each memory cell may be associated with a pair of pages, including a first page belonging to a page group A and a second page belonging to a page group B. According to a predetermined rule, a program speed of pages belonging to the page group A is faster than a program speed of pages belonging to the page group B. In the embodiment of the invention, when the controller 102 determines to access the corresponding memory block in an SLC manner, only one page corresponding to each memory cell is written. As an example, the data may be written to the first page belonging to the page group A with a faster program speed. According to another predetermined rule, the pages belonging to different page groups may have some other different page properties. As an example, an error correcting and checking (ECC) capability of the pages belonging to the page group A may be better than an ECC capability of pages belonging to the page group B. In the embodiment of the invention, when the controller 102 determines to access the corresponding memory block in an SLC manner, only one page corresponding to each memory cell is written. As an example, the data may be written to the first page belonging to the page group A with a better ECC capability. According to yet another embodiment of the invention, the data may be only written to the least significant page, which is used to store the least significant bit (LSB) of the memory cell. However, it is noted that in alternate embodiments, the controller 102 may also program the page belonging to the page group B, the most significant page or the most significant bit (MSB) of the memory cell in the SLC manner, and the invention should not be limited thereto.
According to the embodiments of the invention, by estimating the failure probability of the memory device in advance, the memory block may be transformed into and performs like an SLC memory block before being marked as a defective MLC block. By accessing the memory block in an SLC manner, both the access/program speed and operating lifespan of the memory block become similar to that of an SLC memory block. Thus, the operating lifespan of the memory device is greatly extended.
According to another embodiment of the invention, the SSD drive 100 as shown in
According to the embodiments of invention, a predetermined SLC/MLC ratio may be determined in advance and the controller 102 may transform a predetermined number of MLC memory blocks into SLC-like memory blocks in accordance with the predetermined SLC/MLC ratio. Note that different from the conventional hybrid memory device having an unchangeable fixed SLC/MLC ratio that cannot be changed after leaving the factory, the predetermined SLC/MLC ratio in the embodiments of invention may be dynamically adjusted by the controller 102 according to system requirements, user behavior, software environment, the amount of overall memory blocks, and the amount of defective memory blocks, or others. Therefore, the predetermined number (of SLC-like memory blocks) may be flexibly and dynamically adjusted by the controller 102 in accordance with a predetermined rule.
According to the embodiments of the invention, the predetermined number may be X, where X is a positive integer. Each memory cell of the MLC memory device may be associated with a plurality of pages. Each page may be grouped into one of N page groups in accordance with different page properties, where N is also a positive integer and the page properties may be the program speed, ECC capability, storage bits (MSB or LSB) as previously described, or others. When the memory block can be transformed into the SLC-like memory block, the processor may write desired data in accordance with a write operation corresponding to the memory block in an SLC manner by only writing data to M page group(s), wherein M is also a positive integer and M N. In other words, according to an embodiment of the invention, the controller 102 may transform X MLC memory blocks into SLC-like memory blocks, wherein the X SLC-like memory blocks may be accessed in the SLC manner. Thus, for each memory cell in the SLC-like memory block, only the pages belonging to the M page group(s) will be programmed and accessed, and the pages belonging to the (N−M) page group(s) are left to be un-programmable and/or un-accessible.
As an example, each memory cell of the MLC memory device may be associated with a pair of pages. Therefore, in this example, N=2. The pair of pages may include a first page belonging to a page group A with a program speed faster and/or an ECC capability better than a second page belonging to a page group B. When the MLC memory blocks are transformed into SLC-like memory blocks, only one page per cell may be programmed and accessed. Therefore, in this example, M=1 and either the first page belonging to the page group A or the second page belonging to the page group B may be programmed and accessed after the transformation.
According to yet another embodiment of the invention, the multi-channel MLC memory device 204 as shown in
Note that in the conventional method of random collection of the empty pages, the collected empty pages for one write operation may belong to different page groups (for example, some empty pages may belong to page group A some empty pages may belong to page group B) and have different page properties (for example, different program speeds). Therefore, the overall operation time for each write operation can not be less than the time required for writing the page belonging to page B because even if the write operation in the channels for writing the empty pages belong to page group A have finished, the overall write operation cannot be finished until the write operation in the channels for writing the empty pages belong to page group B have finished. Therefore, comparing with the conventional method of random collection of the empty pages, the proposed method can prevent the write operation (for example, the first write operation shown in
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.
Claims
1. A solid state disk drive, comprising:
- a multiple level cell (MLC) memory device, comprising a plurality of memory blocks each comprising a plurality of memory cells capable of storing more than a single bit of data per cell; and
- a controller, transforming at least one memory block into a single level cell (SLC)-like memory block, and accessing the memory block in an SLC manner.
2. The solid state disk drive as claimed in claim 1, wherein the controller further accesses the memory block, estimates a failure probability of the memory block according to the access operation, and transforms the memory block into an SLC-like memory block when the failure probability thereof exceeds a predetermined threshold.
3. The solid state disk drive as claimed in claim 2, wherein the processor estimates the failure probability of the memory block according to an amount of erase operations performed, a read failure rate, a write failure rate and/or a bit error rate of the memory block.
4. The solid state disk drive as claimed in claim 3, wherein the processor further obtains an erase count representing an amount of erase operations performed of the memory block, determines whether the erase count of the memory block has reached a predetermined erase count threshold, and transforms the memory block into the SLC-like memory block when the erase count of the memory block has reached
5. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether the access operation of the memory block has failed, and transforms the memory block into the SLC-like memory block when the access operation of the memory block has failed.
6. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether a bit error rate (BER) of the memory block corresponding to the access operation exceeds a predetermined BER threshold, and transforms the memory block into the SLC-like memory block when the BER of the memory block exceeds the predetermined BER threshold.
7. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner so that each memory cell of the memory block stores a single bit.
8. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant bits of the memory cells of the memory block.
9. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.
10. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.
11. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant pages of the memory cells of the memory block.
12. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with a first number of pages, each page is grouped into one of a second number of page groups in accordance with different page properties, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing a than the second number, and wherein the second number is a positive integer not less than the third number.
13. The solid state disk drive as claimed in claim 1, wherein the controller further transforms a predetermined number of memory blocks into SLC-like memory blocks, and wherein the predetermined number is dynamically adjusted by the controller in accordance with a predetermined rule.
14. A method for managing a memory device comprising a plurality of memory blocks each with a plurality of memory cells capable of storing more than a single bit of data per cell comprising:
- receiving desired data in accordance with a write operation of the memory device;
- estimating a failure probability of at least one memory block to be written corresponding to the write operation; and
- writing the desired data to the memory cells of the memory block in a single level cell (SLC) manner when the estimated failure probability thereof exceeds a predetermined threshold.
15. The method as claimed in claim 14, further comprising:
- transforming a predetermined number of memory blocks into SLC-like memory blocks; and
- accessing the predetermined number of memory blocks in the SLC manner,
- wherein the predetermined number is adjusted in accordance with a predetermined rule.
16. The method as claimed in claim 14, wherein each of the written memory cells stores a single bit.
17. The method as claimed in claim 14, wherein the desired data is only written to least significant bits of the memory cells.
18. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, and the desired data is only written to the first pages of the memory cells.
19. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and the desired data is only written to the first pages of the memory cells.
20. The method as claimed in claim 14, wherein the desired data is only written to least significant pages of the memory cells.
21. The method as claimed in claim 14, wherein the failure probability is estimated according to an amount of erase operations performed, a read failure rate, a
22. The method as claimed in claim 14, further comprising:
- determining whether an erase count of the memory block has reached a predetermined erase count threshold; and
- writing the desired data to the memory cells of the memory block in the SLC manner when the erase count of the memory block has reached the predetermined erase count threshold.
23. The method as claimed in claim 14, further comprising:
- determining whether a previous write operation or a previous read operation of the memory block has failed; and
- writing the desired data to the memory cells of the memory block in the SLC manner when the previous write operation or the previous read operation has failed.
24. The method as claimed in claim 14, further comprising:
- determining whether a bit error rate (BER) of the memory block has exceeded a predetermined BER threshold; and
- writing the desired data to the memory cells of the memory block in the SLC manner when the BER exceeds the predetermined BER threshold.
25. A solid state disk drive, comprising:
- a multi-channel multiple level cell (MLC) memory device, comprising a plurality of memory modules each comprising a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, and each page is grouped into one of a plurality of page groups in accordance with different page properties; and
- a controller, receiving at least one program command from a host to write desired data to the multi-channel MLC memory device, allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command, and writing the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
26. The solid state disk drive as claimed in claim 25, wherein the page property is a program speed.
27. The solid state disk drive as claimed in claim 25, wherein the page property is an error correcting and checking (ECC) capability.
28. A method for managing a multi-channel memory device comprising a plurality of memory modules each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, comprising:
- grouping each page into one of a plurality of page groups in accordance with different page properties;
- receiving at least one program command to write desired data to the multi-channel MLC memory device;
- allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command; and
- writing the desired data in the empty pages,
- wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
Type: Application
Filed: Mar 11, 2010
Publication Date: Dec 30, 2010
Applicant: MEDIATEK INC. (Hsin-Chu)
Inventors: Po-Wei Chang (Hsinchu County), Kun-Hung Hsieh (Hsinchu County), Li-Chun Tu (Hsinchu City), Ting-Chun Chang (Taipei City), Kuo-Hung Wang (Tainan County)
Application Number: 12/721,692
International Classification: G06F 12/00 (20060101); G11C 29/00 (20060101); G06F 11/00 (20060101); H03M 13/05 (20060101); G06F 11/10 (20060101); G06F 11/28 (20060101);