Abstract: A liquid crystal compound of Formula (1) is provided below: wherein R is hydrogen, linear or branching C1-15 alkyl, linear or branching C1-15 alkyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), linear or branching C2-15 alkenyl, or linear or branching C2-15 alkenyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), A and B are, independently, cyclohexane, cyclohexane (wherein any one of —CH2— is replaced by —O— or —NH—), benzene, or benzene (wherein any one of —CH2? is replaced by —N?), X is a single bond, —CO—O—, —O—CO—, —CH2O—, —OCH2—, —CH2CH2—, —C?C—, —C?C—, —CF2O—, or —OCF2—, Q is oxygen or CH2, Y is CF3, CF2H, or CFH2, L1, L2, and L3 are, independently, hydrogen or fluorine, and m is 0, 1, or 2.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Abstract: A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel cap

Abstract: A liquid crystal compound of Formula (1) is provided. In Formula (1), R is hydrogen, linear or branching C1-15 alkyl, linear or branching C1-15 alkyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), linear or branching C2-15 alkenyl, or linear or branching C2-15 alkenyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), A and B are, independently, cyclohexane, cyclohexane (wherein any one of —CH2— is replaced by —O— or —NH—), benzene, or benzene (wherein any one of —CH2? is replaced by —N?), X is a single bond, —CO—O—, —O—CO—, —CH2O—, —OCH2—, —CH2CH2—, —C?C—, —C?C—, —CF2O—, or —OCF2—, Q is oxygen or CH2, Y is CF3, CF2H, or CFH2, L1, L2, and L3 are, independently, hydrogen or fluorine, and m is 0, 1, or 2.

Abstract: A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Abstract: A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.

Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Abstract: A drawer slide assembly includes an outer slide member securable to a side wall of a piece of furniture. An inner slide member with an inverted U-like shape is securable to a drawer and has two free ends bent inwards and a wave-like portion formed between the two free ends. An intermediate slide member is received in the inner member and defined with three raceways, wherein one raceway is defined between a lateral portion of the intermediate slide member and the wave-like portion, and the other two raceways are symmetrically defined at two opposite sides of the intermediate slide member. Three groups of rolling elements are respectively received in the raceways for slidingly coupling the inner slide member and the intermediate slide member. Axes of the rolling elements constitute a triangle. Whereby, the drawer slide assembly has good upright stability and low elastic deformation.