Abstract: A substrate exposure apparatus, having a line light source and a control system. The line light source has several point light sources. The control system converts the pattern into a timing signal to control the light status and dark status of each point light source. The control system also controls a scan light source to radiate the photoresist on the substrate, so that the photoresist is exposed. Further, in a substrate exposure method, multiple point light sources are arranged as at least one line light source to scan the photoresist once or several times to obtain a better resolution of the pattern transferred to the photoresist.

Abstract: A method and apparatus for estimating burn-in time for integrated circuit die on a wafer employs a reliability testing structure placed in a scribe line area of a wafer to permit improved estimation of burn-in time for integrated circuit on a wafer. Each reliability testing structure has a plurality of evaluation device structures formed on the substrate. Groups of the evaluation device structures are stacked on the surface of the substrate. The device structures are created to permit evaluation of one of a plurality of failure mechanisms of the integrated circuit. A forcing input pad and a sensing output pad are connected through a selection circuit to at least one of the evaluation devices. The selection circuit selects which of the evaluation devices are to receive a stimulus and to transmit a response. The stimulus is activated and the substrate is then stressed.

Abstract: A substrate exposure apparatus, having a line light source and a control system. The line light source has several point light sources. The control system converts the pattern into a timing signal to control the light status and dark status of each point light source. The control system also controls a scan light source to radiate the photoresist on the substrate, so that the photoresist is exposed. Further, in a substrate exposure method, multiple point light sources are arranged as at least one line light source to scan the photoresist once or several times to obtain a better resolution of the pattern transferred to the photoresist.

Abstract: A three-transistor SRAM device are disclosed. The SRAM device has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The source of the NMOS is connected either a constant voltage source or a variable voltage source. An PMOS and the NMOS form a common node A. The drain of the NPMOS is connected to the source of the PMOS to form a common node B. A resister is connected between the nodes A and B. Another NMOS is connected between the node B and a bit line. The gate of this NMOS is controlled by a word line. A capacitor type amplifier may be further connected to the node B to form the data latch of the SRAM.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: A three-transistor SRAM device are disclosed. The SRAM device has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The source of the NMOS is connected either a constant voltage source or a variable voltage source. An PMOS and the NMOS form a common node A. The drain of the NPMOS is connected to the source of the PMOS to form a common node B. A resister is connected between the nodes A and B. Another NMOS is connected between the node B and a bit line. The gate of this NMOS is controlled by a word line. A capacitor type amplifier may be further connected to the node B to form the data latch of the SRAM.

Abstract: A substrate exposure apparatus, having a display apparatus and a control system. The display apparatus is used to display the pattern and to transfer the pattern to the photoresist, and includes a non-self luminescent display or a self-luminescent display. The control system is used to control the pattern displayed on the display apparatus.

Abstract: A substrate exposure apparatus, having a line light source and a control system. The line light source has several point light sources. The control system converts the pattern into a timing signal to control the light status and dark status of each point light source. The control system also controls a scan light source to radiate the photoresist on the substrate, so that the photoresist is exposed. Further, in a substrate exposure method, multiple point light sources are arranged as at least one line light source to scan the photoresist once or several times to obtain a better resolution of the pattern transferred to the photoresist.

Abstract: The actual value of a parameter from a laser range finder to a target is determined by adjusting the measured parameter by a measurement error. The error adjustment is based on the relationship between the intensity of the detected pulse and the expected parameter error. The laser range finder has a laser diode for emitting a laser pulse to a target to produce a reflected pulse, and a detector for receiving the reflected pulse. A measurement circuit is coupled to the detector for determining a measured parameter based on the reflected pulse. An integrator is coupled to the detector for determining the pulse area, and therefore, the intensity of the reflected pulse. A processor is coupled to the measurement circuit and the integrator for adjusting the measured parameter based on the pulse area of the reflected pulse, to provide the actual value of the parameter.

Abstract: An apparatus for measuring the speed of an object includes a first laser source for emitting a first laser plane at an intended path, and a second laser source for emitting a second laser plane at the intended path, with the second laser source positioned from the first laser source at a known distance. The apparatus further includes a detector system positioned to receive a first laser light and a second laser light that have been reflected from the first laser plane and the second laser plane, respectively, upon reflection of the first and second laser planes off the object. The detector system generates a first pulse signal and a second pulse signal, respectively, in response to the receipt of the first and second laser lights, respectively. The apparatus also includes a signal processing circuit coupled to the detector system for calculating the speed of an object passing through the intended path based on the first and second pulse signals generated by the detector system.