Patents by Inventor Kuo Yu Liao
Kuo Yu Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12283637Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: GrantFiled: October 31, 2022Date of Patent: April 22, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20250110314Abstract: An optical image capturing system, along an optical axis from an object side to an image side, includes a lens and an optical filter. The lens has refractive power. The optical filter is adjacent to the lens. The lens and/or the optical filter include or includes at least one visible light absorbing ingredient, absorb or absorbs a visible light with a wavelength range from 400 nm to 700 nm, and allows a light with a wavelength range greater than 800 nm to pass correspondingly. In another embodiment, a plurality of lenses is provided. At least one of the lenses is a filter lens. The filter lens includes the at least one visible light absorbing ingredient, so that the optical image capturing system could absorb the visible light and has a high transmittance of the infrared, thereby improving a light receiving efficiency and a working quality.Type: ApplicationFiled: March 13, 2024Publication date: April 3, 2025Applicant: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.Inventors: YING-JUNG CHEN, KUO-YU LIAO, CHIEN-HSUN LAI
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Publication number: 20250113523Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.Type: ApplicationFiled: December 13, 2024Publication date: April 3, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 12206018Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.Type: GrantFiled: March 24, 2024Date of Patent: January 21, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20240290875Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20240234559Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.Type: ApplicationFiled: March 24, 2024Publication date: July 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 12009415Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: GrantFiled: May 8, 2023Date of Patent: June 11, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 11973133Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.Type: GrantFiled: May 8, 2023Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20230275147Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20230275146Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 11688800Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: GrantFiled: August 16, 2020Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20230048684Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20220181505Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: January 11, 2021Publication date: June 9, 2022Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Patent number: 11296036Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.Type: GrantFiled: August 6, 2020Date of Patent: April 5, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
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Publication number: 20220029005Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: ApplicationFiled: August 16, 2020Publication date: January 27, 2022Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20200365521Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
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Patent number: 10816765Abstract: An optical image capturing system is provided. In order from an object side to an image side, the optical image capturing system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. At least one lens among the first lens to the fifth lens has positive refractive power. The sixth lens may have negative refractive power and an object side and an image side thereof are aspherical wherein at least one surface of the sixth lens has an inflection point. The optical image capturing system has six lenses with refractive power. When meeting some certain conditions, the optical image capturing system may have outstanding light-gathering ability and an adjustment ability about the optical path in order to elevate the image quality.Type: GrantFiled: July 10, 2018Date of Patent: October 27, 2020Assignee: Ability Opto-Electronics Technology Co. Ltd.Inventors: Yeong-Ming Chang, Kuo-Yu Liao, Chien-Hsun Lai, Yao-Wei Liu
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Patent number: 10777508Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.Type: GrantFiled: November 9, 2016Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
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Patent number: 10746964Abstract: An optical image capturing system is provided. In order from an object side to an image side, the optical image capturing system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. At least one lens among the first lens to the fifth lens has positive refractive power. The sixth lens may have negative refractive power and an object side and an image side thereof are aspherical wherein at least one surface of the sixth lens has an inflection point. The optical image capturing system has six lenses with refractive power. When meeting some certain conditions, the optical image capturing system may have outstanding light-gathering ability and an adjustment ability about the optical path in order to elevate the image quality.Type: GrantFiled: July 10, 2018Date of Patent: August 18, 2020Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO. LTD.Inventors: Yeong-Ming Chang, Kuo-Yu Liao, Chien-Hsun Lai, Yao-Wei Liu
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Patent number: 10725267Abstract: A four-piece optical lens for capturing image and a four-piece optical module for capturing image are provided. In order from an object side to an image side, the optical lens along the optical axis includes a first lens with refractive power; a second lens with refractive power; a third lens with refractive power; and a fourth lens with positive refractive power; and at least one of the image-side surface and object-side surface of each of the four lens elements are aspheric. The optical lens can increase aperture value and improve the imagining quality for use in compact cameras.Type: GrantFiled: January 4, 2016Date of Patent: July 28, 2020Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO. LTD.Inventors: Po-Jui Liao, Hung-Wen Lee, Ying Jung Chen, Bo Guang Jhang, Kuo-Yu Liao, Yao Wei Liu, Yeong-Ming Chang