Abstract: A thin-type wide-angle imaging lens assembly comprises a fixing diaphragm and an optical set including five lenses. An arranging order from an object side to an image side is: a first lens; a second lens; a third lens; a fourth lens; a fifth lens; and the fixing diaphragm disposed between an object and the third lens. At least one surface of the first, second, and third lenses is aspheric. At least one surface of the fourth and fifth lenses is aspheric. By the concatenation between the lenses and the adapted curvature radius, thickness, interval, refractivity, and Abbe numbers, the assembly attains a shorter height and a better optical aberration.

Abstract: A thin-type wide-angle imaging lens assembly comprises a fixing diaphragm and an optical set including four lenses. An arranging order from an object side to an image side is: a first lens; a second lens; a third lens; a fourth lens; and the fixing diaphragm disposed between an object and the second lens. By the concatenation between the lenses and the adapted curvature radius, thickness/interval, refractivity, and Abbe numbers, the assembly attains a big diaphragm with ultra-wide-angle, a shorter height, and a better optical aberration.

Abstract: A thin imaging lens assembly with four lenses, having one defined as an object side and an opposite end defined as an image side, and comprising: a lens set, including a first lens, a second lens, a third lens, and a fourth lens that are arranged from the object side to the image side in sequence so as to form an optical structure; and a fixed aperture, deposited between the object side and the image side, wherein the first lens has a positive refractive power around an optical axis thereof; the second lens has a negative refractive power around an optical axis thereof; the third lens has a positive refractive power around an optical axis thereof; and the fourth lens comprises a seventh surface, a convex surface around an optical axis thereof, and an eighth surface, a wavy and concave surface around an optical axis thereof.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval.

Abstract: A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.

Abstract: A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.

Abstract: A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired in the sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. In this way, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.

Abstract: A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired using in sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. Thereby, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.

Abstract: A reference current is generated by inputting an adjusting current, which is about two or three micro amperes larger than the drain current of the NROM cell having a highest threshold voltage of the flash memory, a reference current with an initial value, effectively the same as the drain current of the NROM cell with a lowest threshold voltage. The method involves sensing the difference between the reference current decreasing from its initial value, and the adjusting current under a predetermined memory speed.

Abstract: A method for tracking metal bit line coupling effect in sensing a signal received from an array cell within a memory array is disclosed. The method includes that a reference unit with a reference cell is provided, wherein the reference unit induces coupling effect. Then, the memory array and the reference unit are charged to generate a cell signal having coupling effect and a reference signal having coupling effect. Next, a sensing signal is generated from the difference of the cell signal and the reference signal, whereby the coupling effect is compensated. In the read-out operation of the present invention, because of the closeness of two adjacent metal bit lines, the coupling effect is induced in both memory array and reference unit at the same time, so that the coupling effect is compensated. Therefore, precise read-out operation of data stored in a memory cell is made possible, and the reliability of the device is improved by the present invention.

Abstract: A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and operable in parallel with the registered address path.