Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.

Abstract: A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion.

Abstract: A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

Abstract: A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain.

Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

Abstract: The present disclosure illustrates an optical image capture module comprising an optical lens assembly, an aperture stop and an image plane. The optical lens assembly in order from an object side toward an image side comprising: a first lens element, having positive refractive power and a convex object-side surface adjacent to the optical axis; a second lens element, a third lens element and a fourth lens element which have refractive power adjacent to the optical axis; a fifth lens element having refractive power and a concave image-side surface adjacent to the optical axis; a sixth lens element having negative refractive power and a convex surface image-side surface adjacent to the optical axis, at least one of the object-side surface and image-side surface of the sixth lens element being aspheric and having at least one inflection point located between the optical axis and the peripheral surface.

Abstract: An imaging lens module includes first, second and third optical lenses that are arranged sequentially from an object side to an image side along an optical axis, and a constant-aperture diaphragm disposed between the first and second optical lenses. The first optical lens has a positive refractive power, and the second optical lens has a negative refractive power. The third optical lens has a positive refractive power and has an object-side surface and an image-side surface, At least one of which has at least an inflection point. The imaging lens module satisfies: 0.8TL/Dg1.1, in which, TL is a length from an imaging plane to the object-side surface of the first optical lens, and Dg is a length of a diagonal line of a maximum viewing angle on the imaging plane.

Abstract: A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern.

Abstract: A method for fabricating a display panel includes forming a first patterned conductive layer, a gate insulation layer, a semiconductor channel layer, a first passivation layer, a second patterned conductive layer and a pixel electrode on a first substrate. The first patterned conductive layer includes a gate electrode, and the second patterned conductive layer includes a source electrode, a drain electrode and a data line. The patterns of the gate insulation layer, the first passivation layer and the second patterned conductive layer are defined by an etching process and a lift-off process with the same photomask.

Abstract: The present disclosure illustrates a five-piece imaging lens assembly which includes an aperture stop, an optical lens assembly, an image plane. The optical lens assembly, in order from an object side to an image side, includes a first lens element with positive refractive power adjacent to the optical axis and having a convex object-side surface, a second lens element with negative refractive power adjacent to the optical axis and having a concave object-side surface, a third lens element and a fourth lens element with refractive power adjacent to the optical axis, and a fifth lens element with negative refractive power adjacent to the optical axis and having a convex image-side surface. At least one of the object-side surface and the image-side surface of the fifth lens element has an inflection point. The image plane is for image formation for an object.

Abstract: An aerostatic bearing includes a base having a foundation layer and a plurality of ventilation bodies protruding from the foundation layer, the ventilation bodies being made of a porous material; and a sealing layer covering the base and revealing at least one of the ventilation bodies.

Abstract: The present disclosure illustrates an optical image capture module comprising an optical lens assembly, an aperture stop and an image plane. The optical lens assembly in order from an object side toward an image side comprising: a first lens element, having positive refractive power and a convex object-side surface adjacent to the optical axis; a second lens element, a third lens element and a fourth lens element which have refractive power adjacent to the optical axis; a fifth lens element having refractive power and a concave image-side surface adjacent to the optical axis; a sixth lens element having negative refractive power and a convex surface image-side surface adjacent to the optical axis, at least one of the object-side surface and image-side surface of the sixth lens element being aspheric and having at least one inflection point located between the optical axis and the peripheral surface.

Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.

Abstract: A display panel, which has a display region and a non-display region, includes an active array substrate and an opposite substrate disposed opposite to the active array substrate. The active array substrate includes a substrate, a pixel array, and a driving circuit. The pixel array and the driving circuit are disposed on the substrate, wherein the pixel array is located in the display region and the driving circuit is located in the non-display region. The driving circuit includes a first transparent electrode layer, a second transparent electrode layer, and a dielectric layer. The dielectric layer is located between the first transparent electrode layer and the second transparent electrode layer, wherein the first transparent electrode layer and the second transparent electrode layer are electrically coupled to each other to form at least one transparent capacitor.

Abstract: A pixel structure includes a gate electrode, a gate dielectric layer, a silicon channel layer, a silicon source ohmic contact layer, a silicon drain ohmic contact layer, a source auxiliary ohmic contact layer, a drain auxiliary ohmic contact layer, a transparent conductive portion, a transparent pixel electrode, a source electrode, and a drain electrode. The silicon channel layer is disposed on the gate dielectric layer and above the gate electrode. The silicon source ohmic contact layer, the source auxiliary ohmic contact layer, the transparent conductive portion, and the source electrode are disposed on the silicon channel layer in sequence. The silicon drain ohmic contact layer and the drain auxiliary ohmic contact layer are disposed on the silicon channel layer in sequence. At least a portion of the transparent pixel electrode is disposed between the drain electrode and the drain auxiliary ohmic contact layer.

Abstract: The present disclosure illustrates a five-piece imaging lens assembly which includes an aperture stop, an optical lens assembly, an image plane. The optical lens assembly, in order from an object side to an image side, includes a first lens element with positive refractive power adjacent to the optical axis and having a convex object-side surface, a second lens element with negative refractive power adjacent to the optical axis and having a concave object-side surface, a third lens element and a fourth lens element with refractive power adjacent to the optical axis, and a fifth lens element with negative refractive power adjacent to the optical axis and having a convex image-side surface. At least one of the object-side surface and the image-side surface of the fifth lens element has an inflection point. The image plane is for image formation for an object.

Abstract: An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process.

Abstract: A lens assembly includes a lens set which includes a first lens, a second lens, a third lens and a fourth lens arranged in sequence along an optical axis. The first lens has a positive optical power. The second lens has a positive optical power. The third lens has a negative optical power. The fourth lens has a positive optical power, and has an image-side surface, an object-side surface, and a peripheral surface interconnecting the two. At least one of the object-side and image-side surfaces has an inflection point located between the optical axis and the peripheral surface. The lens assembly satisfies 15<HFOV/f<50, in which, HFOV represents one half of a maximum angle of view of the lens assembly, and f represents a focal length thereof.

Abstract: A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit.