Patents by Inventor Kwan Su SHON

Kwan Su SHON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200388306
    Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.
    Type: Application
    Filed: January 3, 2020
    Publication date: December 10, 2020
    Applicant: SK hynix Inc.
    Inventors: Kwan Su SHON, Dong Hyun KIM, Yo Han JEONG
  • Patent number: 10861518
    Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Kwan Su Shon, Jin Ha Hwang
  • Patent number: 10847194
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Dae Han Kwon, Kwan Su Shon, Soon Ku Kang, Jung Hyun Shin, Doo Bock Lee, Yo Han Jeong, Eun Ji Choi, Tae Jin Hwang
  • Publication number: 20200321039
    Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.
    Type: Application
    Filed: October 18, 2019
    Publication date: October 8, 2020
    Applicant: SK hynix Inc.
    Inventors: Dong Hyun KIM, Kwan Su SHON, Jin Ha HWANG
  • Publication number: 20190287587
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Application
    Filed: November 19, 2018
    Publication date: September 19, 2019
    Inventors: Dong Hyun KIM, Dae Han KWON, Kwan Su SHON, Soon Ku KANG, Jung Hyun SHIN, Doo Bock LEE, Yo Han JEONG, Eun Ji CHOI, Tae Jin HWANG
  • Patent number: 10284156
    Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Eun Ji Choi, Yo Han Jeong, Soon Ku Kang, Woo Jin Kang, Kwan Su Shon, Hyun Bae Lee, Tae Jin Hwang
  • Publication number: 20180294784
    Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.
    Type: Application
    Filed: August 3, 2017
    Publication date: October 11, 2018
    Applicant: SK hynix Inc.
    Inventors: Dong Hyun KIM, Eun Ji CHOI, Yo Han JEONG, Soon Ku KANG, Woo Jin KANG, Kwan Su SHON, Hyun Bae LEE, Tae Jin HWANG
  • Patent number: 10097384
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Patent number: 10091032
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Patent number: 10083763
    Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Wook Jang, Kwan Su Shon, Yo Han Jeong
  • Publication number: 20180114586
    Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.
    Type: Application
    Filed: February 3, 2017
    Publication date: April 26, 2018
    Applicant: SK hynix Inc.
    Inventors: Dong Wook JANG, Kwan Su SHON, Yo Han JEONG
  • Patent number: 9859910
    Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Soon Ku Kang, Kwan Su Shon, Yo Han Jeong, Eun Ji Choi
  • Publication number: 20170324592
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Applicant: SK hynix Inc.
    Inventors: Kwan Su SHON, Yo Han JEONG
  • Publication number: 20170324593
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Applicant: SK hynix Inc.
    Inventors: Kwan Su SHON, Yo Han JEONG
  • Patent number: 9787506
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 10, 2017
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Publication number: 20170063577
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Application
    Filed: December 31, 2015
    Publication date: March 2, 2017
    Inventors: Kwan Su SHON, Yo Han JEONG
  • Publication number: 20170019091
    Abstract: A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes.
    Type: Application
    Filed: December 15, 2015
    Publication date: January 19, 2017
    Inventor: Kwan Su SHON
  • Patent number: 9531365
    Abstract: A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventor: Kwan Su Shon
  • Patent number: 9478267
    Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 25, 2016
    Assignee: SK hynix Inc.
    Inventors: Yo Han Jeong, Kwan Su Shon
  • Publication number: 20160006432
    Abstract: A semiconductor device includes a plurality of impedance providing sections suitable for providing an input/output node with a first impedance corresponding to a signal transmission, and a second impedance corresponding to a signal reception, and an impedance control section suitable for adjusting the first impedance by adjusting the number of enabled impedance providing sections among the plurality of impedance providing sections during the signal transmission, and adjusting the second impedance by changing impedance of one or more impedance providing sections among the plurality of impedance providing sections during the signal reception.
    Type: Application
    Filed: December 12, 2014
    Publication date: January 7, 2016
    Inventor: Kwan-Su SHON