Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes.

Abstract: A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes.

Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

Abstract: A semiconductor device includes a plurality of impedance providing sections suitable for providing an input/output node with a first impedance corresponding to a signal transmission, and a second impedance corresponding to a signal reception, and an impedance control section suitable for adjusting the first impedance by adjusting the number of enabled impedance providing sections among the plurality of impedance providing sections during the signal transmission, and adjusting the second impedance by changing impedance of one or more impedance providing sections among the plurality of impedance providing sections during the signal reception.

Abstract: A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signal's, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals.

Abstract: A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.

Abstract: An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals.