Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.

Abstract: The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.

Abstract: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.

Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.

Abstract: In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal and holds a result of the sampling. The delay circuit receives and delays the first clock signal by a predetermined delay time and outputs a second clock signal. The FIFO device processes the result of the sampling output from the first sampling circuit using a FIFO method in response to a first edge of the second clock signal output from the delay circuit.

Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.

Abstract: A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.

Abstract: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.

Abstract: A memory controller with a self-test function includes a test controlling unit configured to generate test data in a test mode, a data transmission unit configured to generate a data read timing signal to transmit the data read timing signal and the generated test data synchronized with the data read timing signal, and a data input/output (I/O) unit configured to feedback the transmitted test data and the transmitted data read timing signal to the data transmission unit, such that the data transmission unit receives fed-back test data and a fed-back data read timing signal. The data transmission unit reads the fed-back test data based on the fed-back data read timing signal, and the test controlling unit compares the fed-back test data with the generated test data. Therefore, the memory controller may perform a fast self-test.

Abstract: The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.

Abstract: Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal. The third logic gate generates a third signal based on either a return signal or an output signal of the second logic gate.

Abstract: A dual data rate (DDR) output circuit has first and second data paths therein that are asymmetric. The first data path is provided through a single-stage latch unit and the second data path is provided through a dual-stage flip-flop device containing a cascaded arrangement of two latch units. The DDR output circuit includes a latch unit, a flip-flop and a buffer circuit. The latch unit is configured to latch-in first data in-sync with a first edge of a clock signal and the flip-flop is configured to latch-in second data in-sync with the first edge of the clock signal. A buffer circuit is also provided. The buffer circuit is electrically coupled to an output of the latch unit and an output of the flip-flop. The buffer circuit is configured to generate the first data at an output terminal of the DDR output circuit in-sync with one edge (e.g. rising or falling) of the clock signal and further configured to generate the second data at the output terminal in-sync with another edge (e.g.

Abstract: A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connected to a first output signal, and a gate connected to a second input signal. The PMOS transistor has a source connected to the first input signal, a drain connected to a second output signal, and a gate connected to the second input signal. The first inverter receives the first output signal and outputs the second output signal. The second inverter receives the second output signal and outputs the first output signal.

Abstract: A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.

Abstract: Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adjustable delay cell that delay transmission through the set delay cells of an input signal to the respective set delay cells an amount that does not vary responsive to the control signal. Delay cells that have an adjustable delay time are also provided.

Abstract: A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first data and the second data, and connecting or disconnecting the first node and the second node, a charge unit connected between the first node and a first voltage and charging the first node with the first voltage, and a power connection controller disconnecting the second node and a second voltage in a first mode in response to a predetermined control signal and connecting the second node and the second voltage in a second mode, wherein the first node is charged with the first voltage in the first mode and the voltage level of the first node is output as a comparison result in the second mode.

Abstract: A memory controller with a self-test function includes a test controlling unit configured to generate test data in a test mode, a data transmission unit configured to generate a data read timing signal to transmit the data read timing signal and the generated test data synchronized with the data read timing signal, and a data input/output (I/O) unit configured to feedback the transmitted test data and the transmitted data read timing signal to the data transmission unit, such that the data transmission unit receives fed-back test data and a fed-back data read timing signal. The data transmission unit reads the fed-back test data based on the fed-back data read timing signal, and the test controlling unit compares the fed-back test data with the generated test data. Therefore, the memory controller may perform a fast self-test.

Abstract: In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal and holds a result of the sampling. The delay circuit receives and delays the first clock signal by a predetermined delay time and outputs a second clock signal. The FIFO device processes the result of the sampling output from the first sampling circuit using a FIFO method in response to a first edge of the second clock signal output from the delay circuit.

Abstract: Arbitration for a communications channel can be provided by scheduling a grant for future access to one of a plurality of requestors to a communications channel shared by the plurality of requestors based on an indication of which of the plurality of requestors is granted access to the communications channel during a current access.

Abstract: In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).