Patents by Inventor Kwan-Yong Lim

Kwan-Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6642132
    Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: November 4, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung Jae Cho, Dae Gyu Park, Kwan Yong Lim
  • Publication number: 20030100155
    Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 29, 2003
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Dae-Gyu Park, Tae-Ho Cha, In-Seok Yeo
  • Publication number: 20030080387
    Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.
    Type: Application
    Filed: September 25, 2002
    Publication date: May 1, 2003
    Inventors: Heung Jae Cho, Dae Gyu Park, Kwan Yong Lim
  • Publication number: 20030082863
    Abstract: The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.
    Type: Application
    Filed: August 29, 2002
    Publication date: May 1, 2003
    Inventors: Kwan Yong Lim, Heung Jae Cho, Dae Gyu Park, In Seok Yeo
  • Patent number: 6506676
    Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Hynix Semiconductor Inc
    Inventors: Dae Gyu Park, Tae Ho Cha, Se Aug Jang, Heung Jae Cho, Tae Kyun Kim, Kwan Yong Lim, In Seok Yeo, Jin Won Park
  • Patent number: 6448166
    Abstract: The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaOxNy film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO2 or SiON film on the semiconductor substrate, depositing an amorphous TaOxNy film on the SiO2 or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaOxNy film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaOxNy film, and crystallize the amorphous TaOxNy film, and depositing a metal barrier film on the crystallized TaOxNy film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: September 10, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung Jae Cho, Dae Gyu Park, Kwan Yong Lim
  • Publication number: 20020086507
    Abstract: A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.
    Type: Application
    Filed: December 26, 2001
    Publication date: July 4, 2002
    Inventors: Dae Gyu Park, Heung Jae Cho, Kwan Yong lim
  • Publication number: 20020086504
    Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a NMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 4, 2002
    Inventors: Dae Gyu Park, Tae Ho Cha, Se Aug Jang, Heung Jae Cho, Tae Kyun Kim, Kwan Yong Lim, In Seok Yeo, Jin Won Park
  • Publication number: 20020001932
    Abstract: The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaOxNy film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO2 or SiON film on the semiconductor substrate, depositing an amorphous TaOxNy film on the SiO2 or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaOxNy film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaOxNy film, and crystallize the amorphous TaOxNy film, and depositing a metal barrier film on the crystallized TaOxNy film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 3, 2002
    Applicant: Hynix Semiconductor, Inc.
    Inventors: Heung Jae Cho, Dae Gyu Park, Kwan Yong Lim