Patents by Inventor Kwan-Yong Lim

Kwan-Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a fin transistor and method for fabricating the same
    Patent number: 7682911
    Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, Tae-Yoon Kim
  • Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
    Patent number: 7667253
    Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Yong-Soo Kim, Se-Aug Jang, Hyun-Chul Sohn
  • Method for fabricating semiconductor device with interface barrier
    Patent number: 7666785
    Abstract: A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
  • Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel
    Patent number: 7629219
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20090236656
    Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
    Type: Application
    Filed: December 24, 2008
    Publication date: September 24, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Min-Gyu SUNG, Yong-Soo KIM, Kwan-Yong LIM
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTERFACE BARRIER
    Publication number: 20090239376
    Abstract: A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer.
    Type: Application
    Filed: June 30, 2008
    Publication date: September 24, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Yong-Soo Kim, Kwan-Yong Lim
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20090200672
    Abstract: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a WSixNy film or a WSix film by using an ALD process.
    Type: Application
    Filed: April 22, 2009
    Publication date: August 13, 2009
    Inventors: Soo Hyun KIM, Kwan Yong LIM, Baek Mann KIM, Young Jin LEE, Noh Jung KWAK, Hyun Chul SOHN
  • Semiconductor device with multiple gate dielectric layers and method for fabricating the same
    Patent number: 7563726
    Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Kwan-Yong Lim, Seung-Ryong Lee
  • SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND LOW SHEET RESISTANCE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20090166723
    Abstract: A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Kwan-Yong Lim
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20090146246
    Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.
    Type: Application
    Filed: June 5, 2008
    Publication date: June 11, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yun Taek Hwang, Kwan Yong Lim
  • Method of forming tungsten polymetal gate having low resistance
    Patent number: 7541269
    Abstract: A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Soo Hyun Kim, Noh Jung Kwak, Baek Mann Kim, Young Jin Lee, Sun Woo Hwang, Kwan Yong Lim
  • SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20090114981
    Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.
    Type: Application
    Filed: June 29, 2008
    Publication date: May 7, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim, Se-Aug Jang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20090115003
    Abstract: A method for fabricating a semiconductor device includes forming a stacked layer including a tungsten layer, forming a hard mask pattern over the stacked layer, and oxidizing a surface of the hard mask pattern to form a stress buffer layer. A portion of the stacked layer uncovered by the hard mask pattern is removed using the hard mask pattern and the stress buffer layer as an etch mask, thereby forming a first resultant structure. A capping layer is formed over the first resultant structure, the capping layer is etched to retain the capping layer on sidewalls of the first resultant structure, and the remaining portion of the stacked layer uncovered by the hard mask pattern is removed.
    Type: Application
    Filed: December 28, 2007
    Publication date: May 7, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Heung-Jae Cho, Kwan-Yong Lim
  • Method for fabricating semiconductor devices having dual gate oxide layer
    Patent number: 7528042
    Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Dae-Gyu Park, Tae-Ho Cha, In-Seok Yeo
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20090111256
    Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.
    Type: Application
    Filed: June 30, 2008
    Publication date: April 30, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
  • METHOD FOR FABRICATING TUNGSTEN LINE AND METHOD FOR FABRICATING GATE OF SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20090029539
    Abstract: A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 29, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Kwan-Yong Lim
  • SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20080224222
    Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 18, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se-Aug JANG, Heung-Jae CHO, Kwan-Yong LIM, Tae-Yoon KIM
  • SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE
    Publication number: 20080157383
    Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
    Type: Application
    Filed: September 26, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong LIM, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE
    Publication number: 20080160746
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer over a substrate, forming an intermediate structure over the first conductive layer, the intermediate structure formed in a stack structure comprising at least a first metal layer and a nitrogen containing metal silicide layer, and forming a second conductive layer over the intermediate structure.
    Type: Application
    Filed: December 7, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
  • SEMICONDUCTOR DEVICE WITH GATE STRUCTURE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
    Publication number: 20080157205
    Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.
    Type: Application
    Filed: June 20, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim