Patents by Inventor Kwang-Ho Lee

Kwang-Ho Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200218103
    Abstract: A display panel includes a base substrate. A semiconductor layer is disposed on the base substrate. A source electrode and a drain electrode are disposed on the semiconductor layer. A first insulating layer is disposed on both the source electrode and the drain electrode. A data line is disposed on the first insulating layer. The data line is electrically connected to the source electrode via a contact hole penetrating through the first insulating layer.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Kwang Ho LEE, Yeo Geon YOON, Joong Gun CHONG, Yong Hwan SHIN
  • Patent number: 10707229
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Patent number: 10676512
    Abstract: The present disclosure relates to a novel modified RNA polymerase sigma factor A (SigA) polypeptide; a polynucleotide encoding the same; a microorganism containing the polypeptide; and a method for producing L-lysine using the microorganism.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 9, 2020
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Lan Huh, Kwang Ho Lee, Hyung Joon Kim, Jun Ok Moon, Song-Gi Ryu
  • Patent number: 10644028
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Ho Lee, Kwang Ho Kim, Seung Hyun Cho, Ji Hwan Yu
  • Patent number: 10620485
    Abstract: A display panel includes a base substrate. A semiconductor layer is disposed on the base substrate. A source electrode and a drain electrode are disposed on the semiconductor layer. A first insulating layer is disposed on both the source electrode and the drain electrode. A data line is disposed on the first insulating layer. The data line is electrically connected to the source electrode via a contact hole penetrating through the first insulating layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang Ho Lee, Yeo Geon Yoon, Joong Gun Chong, Yong Hwan Shin
  • Patent number: 10539824
    Abstract: A color conversion panel includes a substrate, a first color conversion layer and a second color conversion layer disposed on the substrate, a planarization layer covering the first color conversion layer and the second color conversion layer, and a polarization layer disposed on the planarization layer. An outlet from the planarization layer penetrates the polarization layer.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang Ho Lee, Yeo Geon Yoon
  • Publication number: 20190388664
    Abstract: Provided is a method of controlling local release of target compounds by patterning a hydrogel carrying a bone morphogenetic protein as the target compounds on a nanoporous membrane. The nanoporous membrane is capable of controlling local release of the bone morphogenetic protein as a carrier of the bone morphogenetic protein while performing a basic function of the membrane of preventing infiltration of connective tissue, and thus, there is an advantage in that the nanoporous membrane can facilitate generation of controlled bone in a local region.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 26, 2019
    Inventor: Kwang Ho LEE
  • Publication number: 20190309333
    Abstract: The present invention relates to a novel variant RNA polymerase sigma factor 70 (?70) polypeptide, a polynucleotide encoding the same, a microorganism containing the polypeptide, and a method for producing L-threonine by using the microorganism.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 10, 2019
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Ji Sun LEE, Kwang Ho LEE, Hyo Jin KIM, Keun Chul LEE, Young Bin HWANG
  • Patent number: 10378032
    Abstract: The present disclosure relates to a microorganism of the genus Escherichia producing more L-tryptophan by inactivating the activity of phosphatase. Additionally, the present disclosure relates to a method for producing L-tryptophan using the microorganism of the genus Escherichia.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: August 13, 2019
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Hye Min Park, Baek Seok Lee, Seok Myung Lee, Kyungrim Kim, Kwang Ho Lee, Ki Yong Cheong, Keun Cheol Lee, Hyeongpyo Hong
  • Publication number: 20190214407
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: KWANG HO LEE, Kwang Ho Kim, Seung-Hyun Cho, Ji Hwan Yu
  • Publication number: 20190154167
    Abstract: Provided is a fluid control solenoid valve including: a valve body; a valve seat mounted on a lower portion thereof; a coil mounted on an outer circumferential surface thereof and to which power is applied; a core mounted on an inner surface thereof; a lower plunger movably disposed on the inner surface thereof and formed with an orifice and integrally formed with a tight contact portion to be in tight contact with the valve seat on a bottom surface thereof; and an actuating unit arranged to be linearly moved on an upper side of the lower plunger, actuated by interlocking the lower plunger and formed with an actuating rod which is linearly moved and which is in close contact with the orifice. A fluid flow delay unit is provided on an outer surface of the lower plunger to generate pressure difference between upper and lower portions of the lower plunger.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 23, 2019
    Inventor: Kwang Ho LEE
  • Patent number: 10276591
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Ho Lee, Kwang Ho Kim, Seung Hynu Cho, Ji Hwan Yu
  • Publication number: 20190067320
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 28, 2019
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Patent number: 10202609
    Abstract: Disclosed are a recombinant microorganism having enhanced L-amino acid producibility, wherein the recombinant microorganism is transformed to have an inactivated phage receptor thereof, and a method of producing an L-amino acid using the recombinant microorganism. The use of the recombinant microorganism may enable the production of the L-amino acid in a highly efficient manner.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 12, 2019
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Ji Sun Lee, Chang Il Seo, Ki Yong Cheong, Eun Sung Koh, Do Hyun Kwon, Kwang Ho Lee
  • Publication number: 20190027491
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Application
    Filed: March 28, 2018
    Publication date: January 24, 2019
    Inventors: KWANG HO LEE, Kwang Ho KIM, Seung Hynu CHO, Ji Hwan YU
  • Patent number: 10113191
    Abstract: Disclosed are a recombinant microorganism having enhanced L-amino acid productivity, wherein the recombinant microorganism is transformed to have removed or decreased activity of at least one of adenosine deaminase and AMP nucleosidase, and a method of producing an L-amino acid using the recombinant microorganism. The use of the recombinant microorganism may enable the production of the L-amino acid in a highly efficient manner.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: October 30, 2018
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Eun Sung Koh, Su Yon Kwon, Kwang Ho Lee, Ji Sun Lee, Juno Jang, Keun Cheol Lee, Hyeong Pyo Hong
  • Patent number: 10081822
    Abstract: The present invention relates to a microorganism of the genus Escherichia in which L-tryptophan productivity is improved by inactivating phosphatase activity. Further, the present invention relates to a method for producing L-tryptophan using the microorganism of the genus Escherichia.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 25, 2018
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Seok Myung Lee, Baek Seok Lee, Kyungrim Kim, Kwang Ho Lee, Keun Cheol Lee, Hyeongpyo Hong
  • Patent number: 10041099
    Abstract: The present invention relates to a microorganism able to produce L-threonine or L-tryptophan, and to a method for producing L-threonine or L-tryptophan by using same. More specifically, the present invention relates to: recombinant Escherichia coli which is more efficient in producing L-threonine or L-tryptophan by increasing the ability to produce ATP which is used as the most plentiful energy source in cells when producing L-threonine or L-tryptophan; and a method for producing L-threonine or L-tryptophan by using same.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: August 7, 2018
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Ki Yong Cheong, Seok Myung Lee, Young Bin Hwang, Keun Cheol Lee, Kwang Ho Lee
  • Publication number: 20180217427
    Abstract: A display panel includes a base substrate. A semiconductor layer is disposed on the base substrate. A source electrode and a drain electrode are disposed on the semiconductor layer. A first insulating layer is disposed on both the source electrode and the drain electrode. A data line is disposed on the first insulating layer. The data line is electrically connected to the source electrode via a contact hole penetrating through the first insulating layer.
    Type: Application
    Filed: December 22, 2017
    Publication date: August 2, 2018
    Inventors: KWANG HO LEE, YEO GEON YOON, JOONG GUN CHONG, YONG HAWN SHIN
  • Publication number: 20180127792
    Abstract: The present disclosure relates to a microorganism of the genus Escherichia producing more L-tryptophan by inactivating the activity of phosphatase. Additionally, the present disclosure relates to a method for producing L-tryptophan using the microorganism of the genus Escherichia.
    Type: Application
    Filed: May 10, 2016
    Publication date: May 10, 2018
    Inventors: Hye Min PARK, Baek Seok LEE, Seok Myung LEE, Kyungrim KIM, Kwang Ho LEE, Ki Yong CHEONG, Keun Cheol LEE, Hyeongpyo HONG