Patents by Inventor Kwang Hong Lee
Kwang Hong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12135726Abstract: A method performed by a computing device for generating an identification identifier (ID) according to an embodiment of the present disclosure includes obtaining an instance ID for identifying each of a plurality of service instances, and generating an identification ID for identifying a data item sequentially generated by the respective service instance. The identification ID may include the instance ID, a sequence number, and generation time information.Type: GrantFiled: October 26, 2021Date of Patent: November 5, 2024Assignee: SAMSUNG SDS CO., LTD.Inventors: Jae Hong Kim, Kwang Jae Lee, Gyu Haing Kang
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Patent number: 12123903Abstract: A static electricity visualization apparatus capable of visually identifying a measured level of static electricity is provided.Type: GrantFiled: June 10, 2022Date of Patent: October 22, 2024Assignee: SEMES CO., LTD.Inventors: Jun Ho Oh, Kwang Sup Kim, Jae Hong Kim, Kyung Hun Jang, Young Ho Park, Jong Min Lee, Yeon Chul Song, Sang Min Ha, Ji Hoon Yoo, Myeong Jun Lim
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Patent number: 12068506Abstract: A flexible battery may include: an electrode assembly having one or more unit cells each of the unit cells including a pair of electrode plates having different polarities, a separator interposed between the respective electrode plates and electrode tabs that protrude from the respective electrode plates; a pair of electrode leads connected to electrode tabs; and a strengthening tab fixed on any one electrode lead connection tab among the electrode tabs.Type: GrantFiled: April 19, 2022Date of Patent: August 20, 2024Assignees: LIBEST INC., KHVATEC CO., LTD.Inventors: Joo Seong Kim, Jin Hong Ha, Kwang Seok Kim, Gil Ju Lee, Keum Bong Han, Jae Sung Choi, Joon Sik Chung, Hyuk Sang Jo
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Publication number: 20240272475Abstract: The present invention relates to a lighting apparatus using LEDs as light sources and a display using the lighting apparatus, particularly, the present invention provides a lighting apparatus including: a plurality of light sources located on a printed circuit board; and a reflecting unit provided on the printed circuit board; and a spaced area provided inside the reflective unit.Type: ApplicationFiled: April 23, 2024Publication date: August 15, 2024Inventors: Kwang Ho PARK, Chul Hong KIM, Moo Ryong PARK, Byoung Eon LEE
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Publication number: 20240270646Abstract: Provided are a marine concrete composition using dechlorination microorganisms capable of easily removing chlorine generated by seawater through an electrical method by allowing electrons emitted from electricity-generating microorganisms to flow through steel fibers incorporated into ultra-high-performance concrete (UHPC) or high-performance fiber reinforced concrete (HPFRCC) through a dechlorination microbial capsule carrier and capable of self-healing concrete crack sites through a self-healing microbial capsule carrier and is also capable of fundamentally solving the problem of reduced durability against salt damage of ultra-high-performance concrete or high-performance fiber reinforced concrete for application in marine construction environments through a dechlorination microbial capsule carrier, and a method for constructing a marine concrete structure using the same.Type: ApplicationFiled: November 6, 2023Publication date: August 15, 2024Applicants: KOREA INSTITUTE OF CIVIL ENGINEERING AND BUILDING TECHNOLOGY, Four-m Co., Ltd.Inventors: Kyong-Chul Kim, Kwang-Mo Lim, Kyung-Taek Koh, Gum-Sung Ryu, Sung Yong Park, Jae-Yoon Kang, Gi-Hong An, Kihyon Kwon, Nam-Kon Lee, Soonku Yoon, Jueng wan Go, Dong ha Lee
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Patent number: 11901186Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.Type: GrantFiled: February 19, 2019Date of Patent: February 13, 2024Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
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Publication number: 20200388501Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.Type: ApplicationFiled: February 19, 2019Publication date: December 10, 2020Applicants: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
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Patent number: 10847553Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: GrantFiled: January 12, 2018Date of Patent: November 24, 2020Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Eugene A. Fitzgerald, Siau Ben Chiah, Joseph Sylvester Chang, Yong Qu, Wei Shu, Kwang Hong Lee, Bing Wang
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Patent number: 10672608Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: GrantFiled: January 20, 2017Date of Patent: June 2, 2020Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Patent number: 10598853Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.Type: GrantFiled: February 10, 2017Date of Patent: March 24, 2020Assignees: NANYANG TECHNOLOGICAL UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Chuan Seng Tan, Wei Li, P Anantha, Kwang Hong Lee, Shuyu Bao, Lin Zhang
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Patent number: 10510560Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.Type: GrantFiled: August 31, 2016Date of Patent: December 17, 2019Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
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Publication number: 20190355766Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: ApplicationFiled: January 12, 2018Publication date: November 21, 2019Inventors: Li ZHANG, Eng Kian, Kenneth LEE, Soo Jin CHUA, Eugene A. FITZGERALD, Siau Ben CHIAH, Joseph Sylvester CHANG, Yong QU, Wei SHU, Kwang Hong LEE, Bing WANG
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Patent number: 10483351Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.Type: GrantFiled: September 2, 2016Date of Patent: November 19, 2019Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao
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Patent number: 10418273Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.Type: GrantFiled: October 11, 2016Date of Patent: September 17, 2019Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
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Publication number: 20190074214Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.Type: ApplicationFiled: October 11, 2016Publication date: March 7, 2019Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
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Publication number: 20190051516Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: ApplicationFiled: January 20, 2017Publication date: February 14, 2019Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Publication number: 20190035628Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.Type: ApplicationFiled: January 19, 2017Publication date: January 31, 2019Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
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Publication number: 20190033523Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.Type: ApplicationFiled: February 10, 2017Publication date: January 31, 2019Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Chuan Seng TAN, Wei LI, P ANANTHA, Kwang Hong LEE, Shuyu BAO, Lin ZHANG
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Publication number: 20180330982Abstract: A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250° C. to 1000° C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.Type: ApplicationFiled: November 10, 2016Publication date: November 15, 2018Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Eng Kian Kenneth Lee, David Kohen
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Publication number: 20180277629Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.Type: ApplicationFiled: September 2, 2016Publication date: September 27, 2018Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao