Patents by Inventor Kwang Hong Lee

Kwang Hong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180254197
    Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 6, 2018
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
  • Patent number: 10049916
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Yew Heng Tan, Gang Yih Chong, Eugene A. Fitzgerald, Shuyu Bao
  • Patent number: 10049947
    Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
  • Publication number: 20170271201
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 21, 2017
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Yew Heng Tan, Gang Yih Chong, Eugene A. Fitzgerald, Shuyu Bao
  • Publication number: 20170200648
    Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.
    Type: Application
    Filed: July 6, 2015
    Publication date: July 13, 2017
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee