Abstract: Provided are an electrode assembly, a battery, and a battery pack and vehicle including the same. An electrode assembly, in which a first electrode, a second electrode, and a separator interposed therebetween are wound about an axis to define a core and an outer circumferential surface. At least one of the first electrode and the second electrode includes, at a long side end portion, an uncoated portion exposed beyond the separator in a direction of the axis. At least a part of the uncoated portion is bent in a radial direction of the electrode assembly to define a bent surface region having overlapping layers of the uncoated portion. The bent surface region includes a welding target region having a number of the overlapping layers of the uncoated portion, and the welding target region extends along a radial direction of the electrode assembly.

Abstract: An image processing system includes an image sensor suitable for performing an operation in a first mode to generate an image of a first quality and performing an operation in a second mode to generate an image of a second quality which is higher than the first quality; an auxiliary processor suitable for processing the image of the first quality generated by the image sensor in the first mode; and a main processor suitable for processing the image of the second quality generated by the image sensor in the second mode.

Abstract: An image sensor for reducing a sampling time by shortening a stabilization duration is provided. The image sensor includes a pixel unit, a sampling unit sampling a signal from an output node of the pixel unit, a sinking unit sinking current from the output node of the pixel unit, and a current controller controlling the amount of current in the sinking unit.

Abstract: There is provided an image sensor, including an input control unit configured to control signal paths between a plurality of pixels and a plurality of sampling units and supplying outputs from the plurality of pixels in row units to the plurality of sampling units during a normal operation, while supplying the outputs from the plurality of pixels by color, to the plurality of sampling units during a binning operation; and an output control unit configured to control signal paths between the plurality of sampling units and an amplification unit and sequentially supplying outputs from the plurality of sampling units to the amplification unit during the normal operation while simultaneously supplying the outputs from the plurality of sampling units to the amplification unit during the binning operation.

Abstract: An image sensor includes a dummy pixel array with at least one dummy pixel, a pixel array with a plurality of main pixels, and a data processing unit configured to process a signal provided from the main pixels. The dummy pixel includes: a first switch having a first terminal receiving a first voltage and a second terminal coupled to a floating node; a second switch having a first terminal receiving a second voltage; a third switch coupled between a second terminal of the second switch and the floating node; and a driving element configured to drive a first terminal thereof according to a voltage level applied to the floating node.

Abstract: A DLL circuit includes a duty ratio correction unit that corrects the duty ratios of first and second delay clocks duty ratio to generate first and second correction clocks. A duty ratio detection unit detects the duty ratios of the first and second correction clocks, thereby generating first and second detection signals. A voltage comparison unit compares the levels of the first and second detection signals, thereby generating a first fine control signal. An operation mode setting unit generates a locking completion signal and a second fine control signal. A switching unit selectively transmits the first fine control signal or the second fine control signal to a delay control unit according to whether or not the locking completion signal is enabled.

Abstract: An image sensor for reducing a sampling time by shortening a stabilization duration is provided. The image sensor includes a pixel unit, a sampling unit sampling a signal from an output node of the pixel unit, a sinking unit sinking current from the output node of the pixel unit, and a current controller controlling the amount of current in the sinking unit.

Abstract: A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

Abstract: There is provided an image sensor, including an input control unit configured to control signal paths between a plurality of pixels and a plurality of sampling units and supplying outputs from the plurality of pixels in row units to the plurality of sampling units during a normal operation, while supplying the outputs from the plurality of pixels by color, to the plurality of sampling units during a binning operation; and an output control unit configured to control signal paths between the plurality of sampling units and an amplification unit and sequentially supplying outputs from the plurality of sampling units to the amplification unit during the normal operation while simultaneously supplying the outputs from the plurality of sampling units to the amplification unit during the binning operation.

Abstract: Provided is an image sensor including a plurality of sampling units, a plurality of signal lines connected to an amplification unit; and a plurality of first switches positioned between the plurality of sampling units and the plurality of signal lines, connecting a plurality of sampling units to the plurality of signal lines when performing analog binning operation, and connecting one of the plurality of sampling units to one of the signal lines when performing a general operation.

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract: An image sensor includes a dummy pixel array with at least one dummy pixel, a pixel array with a plurality of main pixels, and a data processing unit configured to process a signal provided from the main pixels. The dummy pixel includes: a first switch having a first terminal receiving a first voltage and a second terminal coupled to a floating node; a second switch having a first terminal receiving a second voltage; a third switch coupled between a second terminal of the second switch and the floating node; and a driving element configured to drive a first terminal thereof according to a voltage level applied to the floating node.

Abstract: In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal and a second signal synchronized with a data strobe signal, and the data alignment signal generating unit outputs one of the first signal and the second signal as a data alignment signal in response to the test mode signal. A data alignment unit is synchronized with the data alignment signal to align the data delayed in the data delay unit. The data input apparatus improves the setup/hold window when a semiconductor memory device is in the test mode.

Abstract: A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

Abstract: A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract: A delay circuit includes a delay line unit including a plurality of delay units configured to generate a plurality of delay input clocks by delaying an input clock by a unit delay amount in response to at least one delay control signal; and a signal selection unit configured to selectively output at least one of the plurality of delay input clocks in response to the delay control signal.

Abstract: An image data processing method includes obtaining pixel data from a pixel array and generating image data by rearranging the pixel data.

Abstract: A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.