Abstract: The present invention relates to a delay fixing loop circuit including a delay fixing loop for reducing a skew between an external clock and a data, or between an external clock and an internal clock, and a clock locking method thereof. The delay fixing loop circuit includes a delay circuit delaying a reference clock in which an external clock is buffered and outputting the delayed reference clock as an internal clock; a control circuit comparing the reference clock and a phase of a feedback clock of the internal clock, and increasing or decreasing delay of the reference clock of the delay circuit according to the comparison result if a delay fixing loop is in an enable state, and decreasing delay of the reference clock of the delay circuit according to a reset signal provided from outside if the delay fixing loop is in a disable state; and a clock driver providing the internal clock of the delay circuit which is controlled by the control circuit as an output clock of the delay fixing loop.

Abstract: A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.

Abstract: A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an output clock; a phase splitter for generating a rising and a falling clocks by phase-splitting the output clock; a DCC pumping unit for generating a rising and a falling duty ratio correction signals according to a reset signal; a voltage comparing unit for generating counting increase and decrease signals according to a result of comparing the rising and the falling duty ratio correction signals in response to a comparison control signal; a comparison control unit for generating the comparison control signal and the reset signal; and a counter for increasing/decreasing a value of the count signal according to the counting increase and decrease signals.

Abstract: The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

Abstract: A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch unit latches data input every rising edge of the first pulse, latches data input every rising edge of the second pulse and the latched data, respectively, and allocates the latched data to first and second data lines. The output latch unit latches data, which are firstly allocated to the first and second data lines, in response to a first control signal, and latches data, which are secondly allocated to the first and second data lines, in response to a second control signal.

Abstract: A pumping circuit of a semiconductor device includes a power supply unit for supplying a power source voltage to a first node, a first transfer pump for transferring a first electric potential of the first node to a second node, a first pumping unit coupled to the first node for pumping the power source voltage applied to the first node, a first pump control unit for controlling a voltage applied to a gate of the first transfer pump, a second transfer pump for transferring a second electric potential of the second node to a high voltage output terminal, a second pumping unit coupled to the second node for selectively pumping the second electric potential of the second node, and a second pump control unit for controlling a voltage applied to a gate of the second transfer pump in response to the power source voltage level. If the power source voltage is higher than a predetermined voltage, the first pumping unit performs a pumping operation, and the second pumping unit performs only an on or off operation.

Abstract: A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an output clock; a phase splitter for generating a rising and a falling clocks by phase-splitting the output clock; a DCC pumping unit for generating a rising and a falling duty ratio correction signals according to a reset signal; a voltage comparing unit for generating counting increase and decrease signals according to a result of comparing the rising and the falling duty ratio correction signals in response to a comparison control signal; a comparison control unit for generating the comparison control signal and the reset signal; and a counter for increasing/decreasing a value of the count signal according to the counting increase and decrease signals.

Abstract: Disclosed herein is a pumping circuit of a semiconductor device. According to the pumping circuit in accordance with the present invention, if an externally applied voltage detected by a voltage level detector is below a predetermined voltage, a first transfer pump and a second transfer pump performs a two-step pumping operation without a voltage drop in the first transfer pump and the second transfer pump. If the externally applied voltage detected by the voltage level detector is over a predetermined voltage, the first transfer pump performs a one-step pumping operation without a voltage drop in the first transfer pump, and the second transfer pump performs only an on/off operation without a voltage drop, thus outputting a high voltage to a high voltage output terminal. Accordingly, the present invention is advantageous in that the pumping circuit consumes less current and operates at high efficiency.

Abstract: A pulse generating circuit for self refresh including a voltage comparison unit having a plurality of selectable capacitor charged by a feedback voltage variably supplied through a first node depending on temperature change, for comparing the charge voltage with a reference voltage to output a signal corresponding to the comparison result, a delay circuit connected to the output of the voltage comparison unit, a control unit for receiving the output of the delay circuit, and a temperature sensor connected to the output of the control circuit and providing feedback signal to the voltage comparison unit.

Abstract: A method for forming a semiconductor device, which features omitting a separated procedure for forming a barrier layer by molding a bottom electrode of a capacitor with TiN compounds. The method for forming a bottom electrode of a capacitor with little roughness on the surface by skipping the etching step for patterning on a metallic layer includes: molding a storage node hole to expose the plug by forming a sacrificial layer on the semiconductor substrate where transistors and plugs are formed and etching the sacrificial layer optionally; and by embedding TiN in the storage node hole and separating the neighboring bottom electrodes in the chemical-mechanical polishing method or etch back.

Abstract: A method for forming a capacitor of a semiconductor device having a dielectric film of high dielectric constant having three-dimensional structure for securing capacitance of semiconductor device in order to have excellent deposition characteristics, by forming a storage electrode formed of Ru film on a semiconductor substrate and forming dielectric films formed of high dielectric constant materials having excellent step coverage on the surface of the storage electrode, the dielectric films having a stacked structure of a first dielectric film formed at low deposition speed and a second dielectric film formed at higher deposition speed by reducing the amount of added gas, thereby performing the subsequent process easily and improving yield and productivity of semiconductor device and then embodying high integration of semiconductor device.

Abstract: Disclosed herein is a method for the fabrication of a capacitor of semiconductor device, which is capable of increasing a charge storage capacitance of the capacitor while generation of leakage current in the capacitor. The method comprises the steps of: forming a ruthenium film as a lower electrode on a semiconductor substrate; forming a TaON film having a high dielectric constant on the ruthenium film; and forming a upper electrode on the TaON film.

Abstract: A method for forming a capacitor of a semiconductor device having a dielectric film of high dielectric constant having three-dimensional structure for securing capacitance of semiconductor device in order to have excellent deposition characteristics, by forming a storage electrode formed of Ru film on a semiconductor substrate and forming dielectric films formed of high dielectric constant materials having excellent step coverage on the surface of the storage electrode, the dielectric films having a stacked structure of a first dielectric film formed at low deposition speed and a second dielectric film formed at higher deposition speed by reducing the amount of added gas, thereby performing the subsequent process easily and improving yield and productivity of semiconductor device and then embodying high integration of semiconductor device.

Abstract: A method for forming a semiconductor device, which features omitting a separated procedure for forming a barrier layer by molding a bottom electrode of a capacitor with TiN compounds. The method for forming a bottom electrode of a capacitor with little roughness on the surface by skipping the etching step for patterning on a metallic layer includes: molding a storage node hole to expose the plug by forming a sacrificial layer on the semiconductor substrate where transistors and plugs are formed and etching the sacrificial layer optionally; and by embedding TiN in the storage node hole and separating the neighboring bottom electrodes in the chemical-mechanical polishing method or etch back.

Abstract: Disclosed herein is a method for the fabrication of a capacitor of semiconductor device, which is capable of increasing a charge storage capacitance of the capacitor while generation of leakage current in the capacitor. The method comprises the steps of: forming a rubidium film as a lower electrode on a semiconductor substrate; forming a TaON film having a high dielectric constant on the rubidium film; and forming a upper electrode on the TaON film.

Abstract: There is provided a method for fabricating a capacitor of semiconductor memory device, which can prevent Ti from diffusing into the ferroelectric layer of capacitor from the Ti adhesive layer, which is formed at the time of metal wiring to decrease the contact resistance between the upper electrode of capacitor and the metal wire. In order to prevent diffusion of Ti into the inside of the capacitor, a dense oxide layer is formed on the ferroelectric layer such as SBTN.