Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: A display device includes a substrate including an emission area and a non-emission area, alignment electrodes arranged to be spaced from each other in a first direction on the substrate and extending in a second direction crossing the first direction, and pixels arranged along the second direction. Pixels adjacent to each other in the second direction from among the pixels may be configured to emit light of different colors. Each of the pixels may include first light emitting elements on the alignment electrodes and arranged along the second direction, second light emitting elements on the alignment electrodes, spaced from the first light emitting elements in the first direction, and arranged along the second direction, a first pixel electrode electrically connected to a first driving power and first ends of the first light emitting elements, a second pixel electrode spaced from the first pixel electrode in the first direction.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: Systems and methods for programming an electronic display in a double-row manner are provided. A system may include processing circuitry that generates image data and an electronic display that programs multiple rows of display pixels with different pixel data of the image data at the same time. This may allow double-row interlaced driving to reduce or eliminate image artifacts due to intra-frame pauses.

Abstract: An electronic display may include a touch sensing system configured to perform touch sensing in an active area of the electronic display and display driver circuitry configured to program display pixels of the active area to emit light. The electronic display may also include the active area. The active area may include a first portion and a second portion that are at least partially electrically separated. The display driver circuitry may program the display pixels in the first portion while the touch sensing circuitry may perform touch sensing in the second portion.

Abstract: A pixel array may be illuminated with backlight illumination from a backlight. The backlight may include a two-dimensional array of light-emitting diodes, with each light-emitting diode being placed in a respective cell. Different light-emitting diodes may have unique brightness magnitudes based on the content of the given display frame. Driver integrated circuits may control one or more associated light-emitting diodes to have a desired brightness level. The driver integrated circuits may be formed in an active area of the backlight. The driver integrated circuits may be arranged in groups that are daisy chained together. A digital signal (that includes information such as addressing information) may be propagated through the group of driver integrated circuits. To manage thermal performance of the backlight, the backlight may include a thermally conductive layer and/or a heat sink structure. To increase the efficiency of the backlight, the backlight may include one or more reflective layers.

Abstract: A pixel array may be illuminated with backlight illumination from a backlight. The backlight may include a two-dimensional array of light-emitting diodes, with each light-emitting diode being placed in a respective cell. Different light-emitting diodes may have unique brightness magnitudes based on the content of the given display frame. Driver integrated circuits may control one or more associated light-emitting diodes to have a desired brightness level. The driver integrated circuits may be formed in an active area of the backlight. The driver integrated circuits may be arranged in groups that are daisy chained together. A digital signal (that includes information such as addressing information) may be propagated through the group of driver integrated circuits. To manage thermal performance of the backlight, the backlight may include a thermally conductive layer and/or a heat sink structure. To increase the efficiency of the backlight, the backlight may include one or more reflective layers.

Abstract: An electronic device may include a display. The display may include display driver circuitry that is configured to provide image data to columns of pixels and gate driver circuitry that is configured to provide control signals to rows of pixels. The display may be operable at a native refresh rate that is equal to the highest refresh rate at which the display has full resolution. The display may also be operable in a high refresh rate mode with a high refresh rate that is twice (or some other scaling factor greater than) the native refresh rate. To enable operation at the high refresh rate mode, vertical resolution of the display may be sacrificed. In other words, rows of pixels may be grouped together into effective rows that are then scanned in sequence. The gate driver circuitry may be formed as thin-film transistor circuitry or from gate driver integrated circuits.

Abstract: A display may have pixels configured to display images. The pixels may be formed from thin-film transistor circuitry on a substrate. Color filter elements formed from colored polymer such as colored photoimageable polymer may be formed on the substrate. A black matrix formed from black photoimageable polymer may have an array of openings. The colored polymer may have first portions that overlap the black matrix and second portions in the openings that form the color filter elements. In some portions of the pixels, the thin-film transistor circuitry may be interposed between the first portions of the colored polymer and the black matrix. In other portions of the pixels, data lines may be formed that are overlapped by the black matrix and that are interposed between the first portions of the colored polymer and the black matrix.

Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

Abstract: A display may have pixels configured to display images. The pixels may be formed from thin-film transistor circuitry on a substrate. Color filter elements formed from colored polymer such as colored photoimageable polymer may be formed on the substrate. A black matrix formed from black photoimageable polymer may have an array of openings. The colored polymer may have first portions that overlap the black matrix and second portions in the openings that form the color filter elements. In some portions of the pixels, the thin-film transistor circuitry may be interposed between the first portions of the colored polymer and the black matrix. In other portions of the pixels, data lines may be formed that are overlapped by the black matrix and that are interposed between the first portions of the colored polymer and the black matrix.

Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.

Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.

Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

Abstract: A liquid crystal display having an outer layer such as a thin-film transistor layer and an inner layer such as a color filter layer may be mounted in a metal device housing. Transparent conductive coating material may be formed on display layers. The transparent conductive coating material may include a layer on the upper surface of the thin-film transistor layer, a layer on the lower surface of the color filter layer, and an edge coating that extends between the upper surface layer and lower surface layer. Electrostatic discharge protection structures for the display may include a conductive elastomeric gasket that couples the upper surface layer to an inner surface of the housing, a conductive tape that couples the lower surface layer to the inner surface, and a conductive material on the inner surface that contacts the edge coating.

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

Abstract: A display may have an active area surrounded by an inactive border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. An upper polarizer may have a polarized central region that overlaps the active area of the display. The upper polarizer may also have an unpolarized portion in the inactive border area overlapping the border structures. The border structures may include colored material such as a white layer on the inner surface of the thin-film transistor layer. Binary information may be embedded into an array of programmable resonant circuits. The binary information may be a display identifier or other information associated with a display. The programmable resonant circuits may be tank circuits with adjustable capacitors, fuses, or other programmable components.

Abstract: A display may have an array of pixels controlled by display driver circuitry. The display driver circuitry may supply the pixels with data signals over data lines in columns of the pixels and may supply the pixels with gate line signals over gate lines in rows of the pixels. The display driver circuitry may have a display driver integrated circuit located on one of the edges of the display. The display driver circuitry may also have gate driver integrated circuits that extend along opposing edges of the display to form a pair of shift registers. Conductive lines in a display substrate may be coupled to opposing ends of the shift registers and to intermediate locations within the shift registers to minimize delays in distributing a gate high voltage signal from the display driver integrated circuit to the shift registers.

Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.