Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract: In a nonvolatile memory device and a method of fabricating the same, the nonvolatile memory device may include a semiconductor substrate having a device isolation layer defining an active region, a pair of nonvolatile memory transistors on the active region, a select transistor disposed between the pair of nonvolatile memory transistors, and floating diffusion regions on the active region between each of the nonvolatile memory transistors and the select transistor. The select transistor may include a gate insulation layer having a thickness and a material that are the same as those of gate insulation layers of the nonvolatile memory transistors. The resulting nonvolatile memory device may include a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: Described are a semiconductor device, methods of forming the semiconductor device and methods of operating the semiconductor device. The semiconductor device includes a gate electrode and laminated charge trap layers interposed between substrates. The methods of forming the semiconductor device include forming a gate stacked structure including insulating layers having a different etching selectivity, forming spaces on sidewalls of the gate stacked structure using an etching selectivity and forming charge trap layers in the spaces. The methods of operating the semiconductor device include programming trap layers by controlling a voltage applied to a gate electrode.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed.

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed.

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.