Patents by Inventor Kwang-Young Jung
Kwang-Young Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974433Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.Type: GrantFiled: January 14, 2022Date of Patent: April 30, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Heon Kang, Tae Hun Kim, Jae Ryong Sim, Kwang Young Jung, Gi Yong Chung, Jee Hoon Han, Doo Hee Hwang
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Publication number: 20240136402Abstract: Silicon carbide power semiconductor device having uniform channel length and manufacturing method thereof disclosed. The power semiconductor device includes a drift region of a first conductivity type, a plurality of body regions of a second conductivity type, being formed to be spaced apart from each other with a preset WS in a horizontal direction in an upper region of the drift region, a JFET region of the first conductivity type and a low-resistance region of the first conductivity type, being formed in a separation space between adjacent body regions to contact their side surfaces with the adjacent body regions and a source region of the first conductivity type, being formed in a surface region in the body region in contact with the low-resistance region to be spaced apart from the low-resistance region by a preset channel length.Type: ApplicationFiled: February 1, 2023Publication date: April 25, 2024Inventors: Kwang Hoon OH, Jin Young Jung, Soo Seong Kim
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Patent number: 11961223Abstract: An apparatus for predicting performance of a wheel in a vehicle: includes a learning device that generates a latent space for a plurality of two-dimensional (2D) wheel images based on a convolutional autoencoder (CAE), extracts a predetermined number of the plurality of 2D wheel images from the latent space, and learns a dataset having the plurality of 2D wheel images and performance values corresponding to the plurality of 2D wheel images; and a controller that predicts performance for the plurality of 2D wheel images based on a performance prediction model obtained by the learning device.Type: GrantFiled: April 20, 2021Date of Patent: April 16, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, SOOKMYUNG WOMEN'S UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Jong Ho Park, Chang Gon Kim, Chul Woo Jung, Sang Min Lee, Min Kyoo Kang, Ji Un Lee, Kwang Hyeon Hwang, Nam Woo Kang, So Young Yoo, Seong Sin Kim, Sung Hee Lee
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Publication number: 20240116897Abstract: The present invention relates to a benzothiazole or benzimidazole derivative, a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising same as an active ingredient for prevention or treatment of SIRTUIN 7 protein-related diseases. With excellent inhibitory activity against SIRTUIN 7 protein the derivative can be used for preventing or treating SIRTUIN 7 protein-related diseases.Type: ApplicationFiled: January 21, 2022Publication date: April 11, 2024Applicant: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Kwang Rok KIM, Kwan Young JEONG, Hee Jung JUNG, Doyoun KIM, Junmi LEE, Sang Dal RHEE, Kyu Myung LEE
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Publication number: 20240065676Abstract: The present disclosure relates to an apparatus for controlling movement of an ultrasonic wave generating unit, the apparatus characterized by comprising: a transfer unit for moving the ultrasonic wave generating unit; and a control unit for controlling the operation of the ultrasonic wave generating unit and the transfer unit, wherein the control unit controls the ultrasonic wave generating unit such that, when the ultrasonic wave generating unit moves, ultrasonic waves are irradiated at intervals to the skin on a movement path of the ultrasonic wave generating unit.Type: ApplicationFiled: October 24, 2023Publication date: February 29, 2024Applicant: JEISYS MEDICAL INC.Inventors: Eun Ho KIM, Kwang Hyeok JUNG, Si Youn KIM, Dong Hwan KANG, Min Young KIM, Hyun Jin KIM, Kwang Ho RYU
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Publication number: 20240035213Abstract: The present invention relates to a multilayer meltblown nonwoven fabric and a method of manufacturing the same. In particular, the present invention relates to a multilayer meltblown nonwoven fabric having excellent lightweightness while exhibiting excellent durability, and a method of manufacturing the same.Type: ApplicationFiled: May 3, 2022Publication date: February 1, 2024Inventors: Seong Su Lim, Kwang Young Jung
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Publication number: 20220139954Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Joo-Heon KANG, Tae Hun KIM, Jae Ryong SIM, Kwang Young JUNG, Gi Yong CHUNG, Jee Hoon HAN, Doo Hee HWANG
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Patent number: 11296110Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.Type: GrantFiled: February 21, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
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Patent number: 11227870Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.Type: GrantFiled: January 10, 2020Date of Patent: January 18, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Heon Kang, Tae Hun Kim, Jae Ryong Sim, Kwang Young Jung, Gi Yong Chung, Jee Hoon Han, Doo Hee Hwang
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Patent number: 10964720Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: GrantFiled: September 22, 2020Date of Patent: March 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
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Patent number: 10950620Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.Type: GrantFiled: January 8, 2019Date of Patent: March 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Young Jung, Dong Won Kim
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Publication number: 20210028190Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: ApplicationFiled: September 22, 2020Publication date: January 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
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Publication number: 20200395377Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.Type: ApplicationFiled: January 10, 2020Publication date: December 17, 2020Inventors: Joo-Heon KANG, Tae Hun KIM, Jae Ryong SIM, Kwang Young JUNG, Gi Yong CHUNG, Jee Hoon HAN, Doo Hee HWANG
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Publication number: 20200388633Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.Type: ApplicationFiled: February 21, 2020Publication date: December 10, 2020Inventors: Kwang Young JUNG, Jong Won KIM, Young Hwan SON, Jee Hoon HAN
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Patent number: 10854631Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: GrantFiled: December 18, 2019Date of Patent: December 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
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Publication number: 20200135761Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: ApplicationFiled: December 18, 2019Publication date: April 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
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Patent number: 10546874Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: GrantFiled: December 14, 2017Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
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Publication number: 20190326318Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.Type: ApplicationFiled: January 8, 2019Publication date: October 24, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kwang Young JUNG, Dong Won KIM
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Publication number: 20180350831Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.Type: ApplicationFiled: December 14, 2017Publication date: December 6, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog EUN
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Patent number: 9773645Abstract: A remote plasma generator includes a body, a driver, and a protection tube. The body includes a gas injection port, a plasma exhaust port, and a plasma generation pipe through which discharge gas or plasma flow. The driver is coupled to the body and generates a magnetic field and plasma in the body. The protection tube is at an inner side of the plasma generation pipe to protect the plasma generation pipe from plasma.Type: GrantFiled: January 29, 2016Date of Patent: September 26, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., DANDAN CO., LTD., NEW POWER PLASMA CO., LTD.Inventors: Ja-woo Lee, Chung-huan Jeon, Heok-jae Lee, Jang-hyoun Youm, Sang-jean Jeon, Kwang-young Jung, Sun-uk Kim, Kang-ho Lee, Jung-hyun Cho, Soon-im Wi, Yun-sik Yang, Moo-jin Kim, Jang-kyu Choi