Patents by Inventor Kwang-Young Jung

Kwang-Young Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964720
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Patent number: 10950620
    Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Young Jung, Dong Won Kim
  • Publication number: 20210028190
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
  • Publication number: 20200395377
    Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.
    Type: Application
    Filed: January 10, 2020
    Publication date: December 17, 2020
    Inventors: Joo-Heon KANG, Tae Hun KIM, Jae Ryong SIM, Kwang Young JUNG, Gi Yong CHUNG, Jee Hoon HAN, Doo Hee HWANG
  • Publication number: 20200388633
    Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.
    Type: Application
    Filed: February 21, 2020
    Publication date: December 10, 2020
    Inventors: Kwang Young JUNG, Jong Won KIM, Young Hwan SON, Jee Hoon HAN
  • Patent number: 10854631
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Publication number: 20200135761
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
  • Patent number: 10546874
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Publication number: 20190326318
    Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.
    Type: Application
    Filed: January 8, 2019
    Publication date: October 24, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kwang Young JUNG, Dong Won KIM
  • Publication number: 20180350831
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: December 14, 2017
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog EUN
  • Patent number: 9773645
    Abstract: A remote plasma generator includes a body, a driver, and a protection tube. The body includes a gas injection port, a plasma exhaust port, and a plasma generation pipe through which discharge gas or plasma flow. The driver is coupled to the body and generates a magnetic field and plasma in the body. The protection tube is at an inner side of the plasma generation pipe to protect the plasma generation pipe from plasma.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: September 26, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DANDAN CO., LTD., NEW POWER PLASMA CO., LTD.
    Inventors: Ja-woo Lee, Chung-huan Jeon, Heok-jae Lee, Jang-hyoun Youm, Sang-jean Jeon, Kwang-young Jung, Sun-uk Kim, Kang-ho Lee, Jung-hyun Cho, Soon-im Wi, Yun-sik Yang, Moo-jin Kim, Jang-kyu Choi
  • Publication number: 20160307739
    Abstract: A remote plasma generator includes a body, a driver, and a protection tube. The body includes a gas injection port, a plasma exhaust port, and a plasma generation pipe through which discharge gas or plasma flow. The driver is coupled to the body and generates a magnetic field and plasma in the body. The protection tube is at an inner side of the plasma generation pipe to protect the plasma generation pipe from plasma.
    Type: Application
    Filed: January 29, 2016
    Publication date: October 20, 2016
    Applicants: DANDAN CO., LTD., New Power Plasma Co., Ltd.
    Inventors: Ja-woo LEE, Chung-huan JEON, Heok-jae LEE, Jang-hyoun YOUM, Sang-jean JEON, Kwang-young JUNG, Sun-uk KIM, Kang-ho LEE, Jung-hyun CHO, Soon-im WI, Yun-sik YANG, Moo-jin KIM, Jang-kyu CHOI
  • Patent number: 5109478
    Abstract: There is provided a circuit for generating a square test pattern including: a clock pulse generator for generating clock pulses; a frequency demultiplier for dividing the clock pulses of the clock pulse generator by eight in order to minimize errors in synchronism; a longitudinal line generator for receiving the divided clock pulses of the frequency demultiplier to generate longitudinal line printing data and a printing start and end signals; a printing area establishing unit for receiving a printing start and end signals of a line output from the longitudinal line generator to establish the printing and end points by the clock pulses of the frequency demultiplier; a synchronizing signal generator for synchronizing horizontal synchronizing signals by the divided clock pulses of the clock pulse generator to generate load signals of the longitudinal line generator and transverse line clock pulses; a transverse line generator for receiving the transverse line clock pulses of the synchronizing signal generator to
    Type: Grant
    Filed: December 31, 1990
    Date of Patent: April 28, 1992
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Kwang-Young Jung