Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: A method of fabricating a high voltage CMOS device is provided that does not require a separate mask for forming a photo align key when forming a high voltage deep well region. The method includes forming a relatively thick first oxide film pattern exposing a predetermined region of a semiconductor substrate; forming a second oxide film pattern on the exposed semiconductor substrate; and forming a high voltage deep well region by performing an ion implant and an annealing using the first oxide film pattern as a mask. The second oxide film pattern is diffused by means of the annealing to generate a step on the high voltage deep well region. The step can be used as a photo align key.

Abstract: A trench gate semiconductor device and a method for fabricating the same, which are capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, are disclosed. Embodiments relate to a method for fabricating a trench gate semiconductor device including forming a trench in an upper surface of an epitaxial layer formed over a semiconductor substrate. N type impurity ions may be implanted into a bottom surface of the trench, to form a diffusion layer. To form a well, P-type impurity ions may be implanted into a region beneath the diffusion layer. To form an oxide film buffer, the trench may be filled with an oxide. To form a gate trench, the resulting structure obtained after the filling of the oxide may be etched from the oxide film buffer to the epitaxial layer, in a region where a gate will be formed. NPN junctions may be formed beneath the oxide film buffer at opposite sides of the gate poly.

Abstract: The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated by a device isolation layer, forming a polysilicon gate on the substrate, forming an insulating layer on the substrate, forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer, forming a P+ ion implanted region in the substrate, forming an N+ ion implanted region in the substrate, and forming silicide on the P+ and N+ ion implanted regions.

Abstract: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

Abstract: A method of fabricating a high voltage CMOS device is provided that does not require a separate mask for forming a photo align key when forming a high voltage deep well region. The method includes forming a relatively thick first oxide film pattern exposing a predetermined region of a semiconductor substrate; forming a second oxide film pattern on the exposed semiconductor substrate; and forming a high voltage deep well region by performing an ion implant and an annealing using the first oxide film pattern as a mask. The second oxide film pattern is diffused by means of the annealing to generate a step on the high voltage deep well region. The step can be used as a photo align key.

Abstract: A semiconductor device including a well region formed in a silicon substrate; a trench exposing a predetermined portion of the uppermost surface of the semiconductor substrate; a body layer formed in the semiconductor substrate at the trench; a device isolation layer formed in the well region; a gate insulating layer formed in the trench over the body layer; a gate electrode formed in the trench over the gate insulating layer and against the device isolation layer; a lightly doped drain region formed in the body layer; an insulating layer formed in the trench over the lightly doped drain region; a source region formed in the body layer; a drain region formed in the well region against the device isolation layer; and a body region formed in the body layer against the source region. The on-resistance can be reduced by forming the gate and source beneath the device isolating layer.

Abstract: A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.

Abstract: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

Abstract: A semiconductor device may include a semiconductor substrate with a well area; a conductive body in the well area; a source in the body; a drift region and a drain in a vertical region of the well area other than the body; and a gate electrode between the source and the drain.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an emitter region of the second conductivity type into the base region; forming an emitter in the emitter region, and forming a collector in the collector region; and forming a base in the semiconductor substrate through implanting high concentration impurity ions of the first conductive type into the semiconductor substrate.

Abstract: The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.

Abstract: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern, and a low-density P type base area may be formed in the semiconductor substrate. Second spacers may be formed on sidewalls of the first spacers. A high-density N type emitter area may be formed in the low-density P type base area between the second spacers, and a high-density N type collector area may be formed in the semiconductor substrate at an outside of the first spacers. The bipolar junction transistor may be realized through a self-aligned scheme using dual nitride spacers. A base width between the emitter area and the low-density collector area may be narrowed by the width of the second spacer.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.