Abstract: Provided is a method of setting criteria for classification of data in an electronic apparatus, the method including identifying a subtask related to data classification, obtaining a plurality of data, based on a model associated with the subtask, obtaining a score associated with the subtask for each of the plurality of data, identifying category information associated with the subtask for each of the plurality of data, and based on the category information and the score, determining a threshold value corresponding to the subtask.

Abstract: An apparatus for molding a pouch includes: a die assembly with a die; a stripper assembly to press and fix both sides of a pouch film disposed on the die; and a punch assembly with a punch to mold an electrode assembly accommodation part in the pouch film. The stripper assembly includes: a stripper disposed at a punch assembly lower portion to press and fix the pouch film; a stripper driving piece at a punch assembly upper portion to provide force so that the stripper presses the pouch film; and a connection part to connect the stripper driving piece to the stripper to transmit the force. The connection part includes: two or more connection rods coupled to the stripper; a connection bar coupled to the stripper driving piece; and a connection piece to connect one or more of the connection rods to the connection bar to transmit the force.

Abstract: Disclosed herein is a pouch-type secondary battery and a manufacturing method thereof including. The pouch-type secondary battery includes an electrode assembly; an electrode lead extending from an electrode tab of the electrode assembly; an upper pouch; and a lower pouch. The upper pouch and the lower pouch include a sealed area where the edges are sealed and an unsealed area. An average thickness of the sealed area of the upper pouch and an average thickness of the sealed area of the lower pouch are equal to each other, and the average thickness of the unsealed area of the upper pouch is smaller than the average thickness of the unsealed area of the lower pouch, so that even if the thickness of the lower pouch is reduced during the sealing process of heat-sealing, the sealed area of the upper and lower pouches are formed with little difference in thickness.

Abstract: A sealing device for a pouch-type battery includes an upper sealing block and a lower sealing block. The upper sealing block has a two-stage upper sealing groove, including a first upper step and a second upper step, and the lower sealing block has a two-stage lower sealing groove, including a first lower step and a second lower step. The upper sealing block contacts a first surface of an electrode lead sealing part of the pouch-type battery, and the lower sealing block contacts a second surface of the electrode lead sealing part of the pouch-type battery in a process of performing sealing through heat fusion. A pouch-type battery having an electrode lead sealing part formed by the sealing device is also provided.

Abstract: A method for training a training dynamics prediction model comprising acquiring classification information on training data included in a first dataset based on a classification model, acquiring target training dynamics information based on the classification information and a set of one or more classification information acquired based on the classification model in one or more previous epochs, acquiring predictive training dynamics information on the training data based on the training dynamics prediction model, and training the training dynamics prediction model based on the target training dynamics information and the predictive training dynamics information is disclosed.

Abstract: The present invention relates to a pouch-shaped battery case sealing apparatus capable of adjusting a direction in which an upper sealing block configured to press a laminate sheet applies pressure to the laminate sheet during a process of applying heat and pressure to an outer periphery of a battery case made of the laminate sheet to seal the outer periphery of the battery case when a pouch-shaped battery is manufactured and a pouch-shaped secondary battery sealing method using the same.

Abstract: Provided is a method for training a model, including generating a plurality of attention maps by inputting training data into a previously trained teacher model, generating a set of attention weights of the teacher model based on the plurality of attention maps, generating a set of attention weights of a student model by inputting the training data into the student model, calculating a value of a first loss function based on the set of attention weights of the teacher model and the set of attention weights of the student model, calculating a value of a second loss function according to an inference of the student model with respect to the training data, and training the student model based on the value of the first loss function and the value of the second loss function.

Abstract: Provided/Disclosed is a cardiopulmonary resuscitation (CPR) training apparatus, comprising: a mannequin including a head portion with an airway, and a body portion connected to the head portion; a compression portion provided in the body portion, the compression portion to be pressed in response to a chest compression; an airbag connected to the airway, the airbag configured to enable an artificial ventilation; and a measurer configured to measure a CPR performance state in response to the chest compression and the artificial ventilation performed on the mannequin.

Abstract: Provided/Disclosed is a cardiopulmonary resuscitation (CPR) training apparatus, comprising: a mannequin including a head portion with an airway, and a body portion connected to the head portion; a compression portion provided in the body portion, the compression portion to be pressed in response to a chest compression; an airbag connected to the airway, the airbag configured to enable an artificial ventilation; and a measurer configured to measure a CPR performance state in response to the chest compression and the artificial ventilation performed on the mannequin.

Abstract: A PCIe capable semiconductor device includes; ports respectively configured to transmit and receive data in a PCIe environment, and a PCIe controller configured to set a link between the PCIe capable semiconductor device and another PCIe capable semiconductor device. The link includes at least one lane implemented over at least one of the ports. The PCIe controller includes a link training and status state machine (LTSSM) configured to perform a first lane number negotiation according to a first ordering of the ports and a second lane number negotiation according to a second ordering of the ports different from the first ordering of the ports, and determine an optimized link width for the link according to the results of the first lane number negotiation and the second lane number negotiation.

Abstract: A PCIe device for supporting SRIS includes a transceiver, a clock signal generator configured to generate a second reference clock signal, a connector in a structure to be connected to a PCIe host, and a selection circuit configured to determine whether a first reference clock signal is supplied through the connector and transmit one of the first reference clock signal and the second reference clock signal to the transceiver according to a result of the determination.

Abstract: Provided/Disclosed is a cardiopulmonary resuscitation (CPR) training apparatus, comprising: a mannequin including a head portion with an airway, and a body portion connected to the head portion; a compression portion provided in the body portion, the compression portion to be pressed in response to a chest compression; an airbag connected to the airway, the airbag configured to enable an artificial ventilation; and a measurer configured to measure a CPR performance state in response to the chest compression and the artificial ventilation performed on the mannequin.

Abstract: A PCIe capable semiconductor device includes; ports respectively configured to transmit and receive data in a PCIe environment, and a PCIe controller configured to set a link between the PCIe capable semiconductor device and another PCIe capable semiconductor device. The link includes at least one lane implemented over at least one of the ports. The PCIe controller includes a link training and status state machine (LTSSM) configured to perform a first lane number negotiation according to a first ordering of the ports and a second lane number negotiation according to a second ordering of the ports different from the first ordering of the ports, and determine an optimized link width for the link according to the results of the first lane number negotiation and the second lane number negotiation.

Abstract: A PCIe device for supporting SRIS includes a transceiver, a clock signal generator configured to generate a second reference clock signal, a connector in a structure to be connected to a PCIe host, and a selection circuit configured to determine whether a first reference clock signal is supplied through the connector and transmit one of the first reference clock signal and the second reference clock signal to the transceiver according to a result of the determination.

Abstract: A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry.

Abstract: Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Abstract: A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry.

Abstract: Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.