Patents by Inventor Kwok Cheung Tsang

Kwok Cheung Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9520306
    Abstract: A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 13, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Geraldine Tsui Yee Lin, Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Patent number: 9449903
    Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 20, 2016
    Assignee: UTAC Hong Kong Limited
    Inventors: Neil McLellan, Ming Wang Sze, Kwok Cheung Tsang, Wing Keung Lam, Wai Kit Tam
  • Patent number: 9373576
    Abstract: An integrated circuit (IC) package substrate is provided. In one embodiment, the IC package substrate includes a dielectric layer having first and second opposing surfaces and a matrix of pillars disposed in the dielectric layer and arranged to receive a matrix of conductive elements of an IC die. Each pillar of the matrix of pillars is exposed at the first surface of the dielectric layer. Each pillar of the matrix of pillars extends through the dielectric layer to contact a metal layer attached to the second surface of the dielectric layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: June 21, 2016
    Assignee: Broadcom Corporation
    Inventor: Kwok Cheung Tsang
  • Publication number: 20160013075
    Abstract: A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 14, 2016
    Inventors: Geraldine Tsui Yee LIN, Walter de MUNNIK, Kin Pui KWAN, Wing Him LAU, Kwok Cheung TSANG, Chun Ho FAN, Neil McLELLAN
  • Publication number: 20150194378
    Abstract: An integrated circuit (IC) package substrate is provided. In one embodiment, the IC package substrate includes a dielectric layer having first and second opposing surfaces and a matrix of pillars disposed in the dielectric layer and arranged to receive a matrix of conductive elements of an IC die. Each pillar of the matrix of pillars is exposed at the first surface of the dielectric layer. Each pillar of the matrix of pillars extends through the dielectric layer to contact a metal layer attached to the second surface of the dielectric layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: Broadcom Corporation
    Inventor: Kwok Cheung TSANG
  • Patent number: 8779598
    Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 15, 2014
    Assignee: Broadcom Corporation
    Inventors: Fan Yeung, Raymond (Kwok Cheung) Tsang, Edward Law
  • Publication number: 20140183712
    Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 3, 2014
    Applicant: UTAC Hong Kong Limited
    Inventors: Neil McLellan, Ming Wang Sze, Kwok Cheung Tsang, Wing Keung Lam, Wai Kit Tam
  • Patent number: 8610262
    Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: December 17, 2013
    Assignee: UTAC Hong Kong Limited
    Inventors: Neil McLellan, Ming Wang Sze, Kwok Cheung Tsang, Wing Keung Lam, Wai Kit Tam
  • Publication number: 20130000968
    Abstract: A method of manufacturing a printed circuit board is disclosed. A conductive metal layer is formed on a first surface of a dielectric substrate. One or more vias are formed through the substrate. A conductive metal layer is formed on the first surface of the substrate and is patterned to form conductive traces on the first surface of the substrate. A plating mask is formed on the second surface of the substrate. One or more openings are formed in the plating mask to correspond to the location of the via(s). Conductive metal is deposited in the via(s) sufficient to substantially fill the via(s) and make contact with the conductive metal layer on the first surface and substantially to the level of the plating mask. The plating mask is removed from the substrate such that one or more conductive posts extend outwardly from the second surface of the substrate.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan, Raymond Kwok Cheung Tsang
  • Publication number: 20130001791
    Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: Broadcom Corporation
    Inventors: Fan YEUNG, Raymond (Kwok Cheung) TSANG, Edward LAW
  • Patent number: 8330270
    Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: December 11, 2012
    Assignee: UTAC Hong Kong Limited
    Inventors: Geraldine Tsui Yee Lin, Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Publication number: 20110284495
    Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.
    Type: Application
    Filed: September 20, 2007
    Publication date: November 24, 2011
    Applicant: ASAT LIMITED
    Inventors: Tung Lok Li, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7482690
    Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers is deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 27, 2009
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang
  • Patent number: 7439099
    Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: October 21, 2008
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow
  • Patent number: 7372151
    Abstract: A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the substrate. The semiconductor die and the solder balls are encapsulated in an overmold material on the substrate such that portions of the solder balls are exposed. A ball grid array is formed such that bumps of the ball grid array are electrically connected to the conductive traces and the integrated circuit package is singulated.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 13, 2008
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Neil McLellan, Kwok Cheung Tsang
  • Patent number: 7358119
    Abstract: A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die is mounted on the substrate such that the contact pads circumscribe the semiconductor die and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds are encapsulated and the semiconductor die and contact pads are covered in a molding material. The substrate is selectively etched to thereby etch away the substrate underneath the contact pads and the semiconductor die. The integrated circuit package is singulated from other integrated circuit packages by sawing using the fiducial markings.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: April 15, 2008
    Assignee: Asat Ltd.
    Inventors: Neil McLellan, Serafin Pedron, Leo M. Higgins, III, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7271032
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: September 18, 2007
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau
  • Patent number: 7270867
    Abstract: A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is selectively deposited on portions of the plurality of layers to further define at least the contact pads. The leadframe strip is then treated with a surface preparation. A semiconductor die is mounted to the die attach pad, followed by wire bonding the semiconductor die to at least the contact pads. Molding the semiconductor die, the wire bonds, the die attach pad and the contact pads on the surface of the leadframe strip, in a molding compound follows. The leadframe strip is etched to expose the contact pads and the die attach pad and the leadless plastic chip carrier is singulated from a remainder of the leadframe strip.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 18, 2007
    Assignee: ASAT Ltd.
    Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Patent number: 7232755
    Abstract: A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: June 19, 2007
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7081403
    Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: July 25, 2006
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan